From patchwork Thu Aug 25 06:21:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 9298839 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1280A608A7 for ; Thu, 25 Aug 2016 07:29:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 04EF8291E1 for ; Thu, 25 Aug 2016 07:29:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ED709291FD; Thu, 25 Aug 2016 07:29:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 542D5291F9 for ; Thu, 25 Aug 2016 07:29:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758100AbcHYH30 (ORCPT ); Thu, 25 Aug 2016 03:29:26 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:49152 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757393AbcHYH3Y (ORCPT ); Thu, 25 Aug 2016 03:29:24 -0400 Received: by wens.csie.org (Postfix, from userid 1000) id B67FD5FA8B; Thu, 25 Aug 2016 14:22:04 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Michael Turquette , Stephen Boyd Cc: Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/6] clk: sunxi-ng: mux: Add support for mux tables Date: Thu, 25 Aug 2016 14:21:56 +0800 Message-Id: <20160825062200.17206-3-wens@csie.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160825062200.17206-1-wens@csie.org> References: <20160825062200.17206-1-wens@csie.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some clock muxes have holes, i.e. invalid or unconnected inputs, between parent mux values. Add support for specifying a mux table to map clock parents to mux values. Signed-off-by: Chen-Yu Tsai --- Changes since v2: - Update macro names as changed in commit ad4578dc4cfa ("clk: sunxi-ng: mux: Rename mux macro to be consistent") - Use _SUNXI_CLK_MUX_TABLE to expand _SUNXI_CLK_MUX Changes since v1: none --- drivers/clk/sunxi-ng/ccu_mux.c | 12 ++++++++++++ drivers/clk/sunxi-ng/ccu_mux.h | 17 +++++++++++------ 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 1329b9ab481e..68b32f168a74 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -107,6 +107,15 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common, parent = reg >> cm->shift; parent &= (1 << cm->width) - 1; + if (cm->table) { + int num_parents = clk_hw_get_num_parents(&common->hw); + int i; + + for (i = 0; i < num_parents; i++) + if (cm->table[i] == parent) + return i; + } + return parent; } @@ -117,6 +126,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, unsigned long flags; u32 reg; + if (cm->table) + index = cm->table[index]; + spin_lock_irqsave(common->lock, flags); reg = readl(common->base + common->reg); diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index 83737c2facd4..b1e085612e5e 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -6,8 +6,9 @@ #include "ccu_common.h" struct ccu_mux_internal { - u8 shift; - u8 width; + u8 shift; + u8 width; + const u8 *table; struct { u8 index; @@ -21,12 +22,16 @@ struct ccu_mux_internal { } variable_prediv; }; -#define _SUNXI_CCU_MUX(_shift, _width) \ - { \ - .shift = _shift, \ - .width = _width, \ +#define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ + { \ + .shift = _shift, \ + .width = _width, \ + .table = _table, \ } +#define _SUNXI_CCU_MUX(_shift, _width) \ + _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL) + struct ccu_mux { u16 reg; u32 enable;