From patchwork Thu Aug 25 19:05:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9299671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3958D607F0 for ; Thu, 25 Aug 2016 19:06:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2CC6D2926C for ; Thu, 25 Aug 2016 19:06:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 20CF4293AD; Thu, 25 Aug 2016 19:06:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C55129290 for ; Thu, 25 Aug 2016 19:06:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751976AbcHYTGF (ORCPT ); Thu, 25 Aug 2016 15:06:05 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:58837 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750971AbcHYTGF (ORCPT ); Thu, 25 Aug 2016 15:06:05 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie2.idc.renesas.com with ESMTP; 26 Aug 2016 04:06:02 +0900 Received: from relmlac1.idc.renesas.com (relmlac1.idc.renesas.com [10.200.69.21]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id A59763F9C0; Fri, 26 Aug 2016 04:06:02 +0900 (JST) Received: by relmlac1.idc.renesas.com (Postfix, from userid 0) id A80E88002E; Fri, 26 Aug 2016 04:06:02 +0900 (JST) Received: from relmlac1.idc.renesas.com (localhost [127.0.0.1]) by relmlac1.idc.renesas.com (Postfix) with ESMTP id A137E8002D; Fri, 26 Aug 2016 04:06:02 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac1.idc.renesas.com with ESMTP id EAD02302; Fri, 26 Aug 2016 04:06:02 +0900 X-IronPort-AV: E=Sophos;i="5.22,559,1449500400"; d="scan'208";a="218650469" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 26 Aug 2016 04:06:01 +0900 Received: from localhost.localdomain (unknown [172.27.49.101]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 7E2442FE; Thu, 25 Aug 2016 19:05:40 +0000 (UTC) From: Chris Brandt To: mturquette@baylibre.com, Stephen Boyd , Geert Uytterhoeven , Simon Horman Cc: Chris Brandt , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH] clk: renesas: rz: Select EXTAL vs USB clock Date: Thu, 25 Aug 2016 15:05:18 -0400 Message-Id: <20160825190518.20764-1-chris.brandt@renesas.com> X-Mailer: git-send-email 2.9.2 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of hard coding EXTAL only, check if EXTAL was specified. If not, then assume the USB clock is used as the main system clock. Signed-off-by: Chris Brandt --- drivers/clk/renesas/clk-rz.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index f6312c6..466b9fc 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c @@ -37,13 +37,29 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 }; if (strcmp(name, "pll") == 0) { - /* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */ - unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */ - const char *parent_name = of_clk_get_parent_name(np, cpg_mode); - - mult = cpg_mode ? (32 / 4) : 30; - - return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1); + u32 freq = 0; + struct device_node *np; + + /* If a clock-frequency for extal was specified, assume EXTAL boot */ + np = of_find_node_by_name(NULL, "extal"); + if( np ) { + of_property_read_u32(np, "clock-frequency", &freq); + if( freq ) + return clk_register_fixed_factor(NULL, "pll", "extal", + 0, 30, 1); + } + + /* Must be USB clock boot */ + np = of_find_node_by_name(NULL, "usb_x1"); + if( np ) { + of_property_read_u32(np, "clock-frequency", &freq); + if( freq ) + return clk_register_fixed_factor(NULL, "pll", "usb_x1", + 0, (32 / 4), 1); + } + + /* No clock frequency set in DT */ + BUG(); } /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */