From patchwork Tue Aug 30 03:13:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9304767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 12657607F0 for ; Tue, 30 Aug 2016 03:15:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B456285CD for ; Tue, 30 Aug 2016 03:15:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00021285F1; Tue, 30 Aug 2016 03:15:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 121D1285CD for ; Tue, 30 Aug 2016 03:15:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755123AbcH3DPL (ORCPT ); Mon, 29 Aug 2016 23:15:11 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:18542 "EHLO relmlie4.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754321AbcH3DPK (ORCPT ); Mon, 29 Aug 2016 23:15:10 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie4.idc.renesas.com with ESMTP; 30 Aug 2016 12:14:35 +0900 Received: from relmlac3.idc.renesas.com (relmlac3.idc.renesas.com [10.200.69.23]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 207EE41B86; Tue, 30 Aug 2016 12:14:35 +0900 (JST) Received: by relmlac3.idc.renesas.com (Postfix, from userid 0) id E582218071; Tue, 30 Aug 2016 12:14:34 +0900 (JST) Received: from relmlac3.idc.renesas.com (localhost [127.0.0.1]) by relmlac3.idc.renesas.com (Postfix) with ESMTP id D542E18070; Tue, 30 Aug 2016 12:14:34 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac3.idc.renesas.com with ESMTP id NAA27111; Tue, 30 Aug 2016 12:14:34 +0900 X-IronPort-AV: E=Sophos;i="5.22,559,1449500400"; d="scan'208";a="218415693" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 30 Aug 2016 12:14:33 +0900 Received: from localhost.localdomain (unknown [143.103.58.80]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id E94DF163; Tue, 30 Aug 2016 03:14:11 +0000 (UTC) From: Chris Brandt To: Geert Uytterhoeven , Sergei Shtylyov , Simon Horman , Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH v2] clk: renesas: rz: Select EXTAL vs USB clock Date: Mon, 29 Aug 2016 23:13:58 -0400 Message-Id: <20160830031358.19468-1-chris.brandt@renesas.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20160825190518.20764-1-chris.brandt@renesas.com> References: <20160825190518.20764-1-chris.brandt@renesas.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Check the MD_CLK pin to determine the current clock mode in order to set the pll clock parent correctly. Signed-off-by: Chris Brandt --- v2: * Switched to reading MD_CLK pin to determine mode --- drivers/clk/renesas/clk-rz.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index f6312c6..2fc8aae 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c @@ -25,6 +25,9 @@ struct rz_cpg { #define CPG_FRQCR 0x10 #define CPG_FRQCR2 0x14 +#define PPR0 0xFCFE3200 +#define PIBC0 0xFCFE7000 + /* ----------------------------------------------------------------------------- * Initialization */ @@ -37,10 +40,20 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 }; if (strcmp(name, "pll") == 0) { - /* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */ - unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */ - const char *parent_name = of_clk_get_parent_name(np, cpg_mode); - + unsigned int cpg_mode; + const char *parent_name; + void __iomem *ppr0, *pibc0; + + /* MD_CLK is on P0_2 */ + ppr0 = ioremap_nocache(PPR0, 2); + pibc0 = ioremap_nocache(PIBC0, 2); + BUG_ON(!ppr0 || !pibc0); + iowrite16(4, pibc0); /* Enable input buffer */ + cpg_mode = ioread16(ppr0) & 4; + iounmap(ppr0); + iounmap(pibc0); + + parent_name = cpg_mode ? "usb_x1" : "extal"; mult = cpg_mode ? (32 / 4) : 30; return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);