From patchwork Thu Sep 1 13:10:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9309033 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 97E54607D6 for ; Thu, 1 Sep 2016 13:13:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A55D293F6 for ; Thu, 1 Sep 2016 13:13:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6F0C6293F7; Thu, 1 Sep 2016 13:13:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22A6A293F6 for ; Thu, 1 Sep 2016 13:13:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932295AbcIANNA (ORCPT ); Thu, 1 Sep 2016 09:13:00 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:20316 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754439AbcIANM6 (ORCPT ); Thu, 1 Sep 2016 09:12:58 -0400 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie1.idc.renesas.com with ESMTP; 01 Sep 2016 22:12:04 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 8851165757; Thu, 1 Sep 2016 22:12:04 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 86A42480A4; Thu, 1 Sep 2016 22:12:04 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 80E88480A3; Thu, 1 Sep 2016 22:12:04 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac4.idc.renesas.com with ESMTP id YAB32230; Thu, 1 Sep 2016 22:12:04 +0900 X-IronPort-AV: E=Sophos;i="5.22,559,1449500400"; d="scan'208";a="218665758" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 01 Sep 2016 22:12:02 +0900 Received: from localhost.localdomain (unknown [172.27.49.101]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 7CCD35B8; Thu, 1 Sep 2016 13:11:30 +0000 (UTC) From: Chris Brandt To: Geert Uytterhoeven , Sergei Shtylyov , Simon Horman , Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH v3] clk: renesas: rz: Select EXTAL vs USB clock Date: Thu, 1 Sep 2016 09:10:36 -0400 Message-Id: <20160901131036.17241-1-chris.brandt@renesas.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20160830031358.19468-1-chris.brandt@renesas.com> References: <20160830031358.19468-1-chris.brandt@renesas.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Check the MD_CLK pin to determine the current clock mode in order to set the pll clock parent correctly. Signed-off-by: Chris Brandt --- v3: * move reading GPIO port into separate function v2: * Switched to reading MD_CLK pin to determine mode --- drivers/clk/renesas/clk-rz.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index f6312c6..29a8638 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c @@ -25,10 +25,34 @@ struct rz_cpg { #define CPG_FRQCR 0x10 #define CPG_FRQCR2 0x14 +#define PPR0 0xFCFE3200 +#define PIBC0 0xFCFE7000 + +#define MD_BOOT0(x) ((x >> 0) & 1) /* P0_0 */ +#define MD_BOOT1(x) ((x >> 1) & 1) /* P0_1 */ +#define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */ +#define MD_CLKS(x) ((x >> 3) & 1) /* P0_3 */ + /* ----------------------------------------------------------------------------- * Initialization */ +u16 rz_cpg_read_mode_pins(void) +{ + void __iomem *ppr0, *pibc0; + u16 modes; + + ppr0 = ioremap_nocache(PPR0, 2); + pibc0 = ioremap_nocache(PIBC0, 2); + BUG_ON(!ppr0 || !pibc0); + iowrite16(4, pibc0); /* enable input buffer */ + modes = ioread16(ppr0); + iounmap(ppr0); + iounmap(pibc0); + + return modes; +} + static struct clk * __init rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) { @@ -37,10 +61,11 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 }; if (strcmp(name, "pll") == 0) { - /* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */ - unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */ - const char *parent_name = of_clk_get_parent_name(np, cpg_mode); + unsigned int cpg_mode; + const char *parent_name; + cpg_mode = MD_CLK(rz_cpg_read_mode_pins()); + parent_name = of_clk_get_parent_name(np, cpg_mode); mult = cpg_mode ? (32 / 4) : 30; return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);