From patchwork Wed Oct 19 13:28:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 9384169 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 066DB608A7 for ; Wed, 19 Oct 2016 14:32:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA7E829A43 for ; Wed, 19 Oct 2016 14:32:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DEED1298A8; Wed, 19 Oct 2016 14:32:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6909D296E4 for ; Wed, 19 Oct 2016 14:32:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S942157AbcJSOcb (ORCPT ); Wed, 19 Oct 2016 10:32:31 -0400 Received: from mail-lf0-f48.google.com ([209.85.215.48]:34599 "EHLO mail-lf0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S941306AbcJSOca (ORCPT ); Wed, 19 Oct 2016 10:32:30 -0400 Received: by mail-lf0-f48.google.com with SMTP id b81so27294572lfe.1 for ; Wed, 19 Oct 2016 07:32:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6WeZp2xSEO9KMoHBSdNPIoAis3aVnYcTFVvYqbzv6U4=; b=ZGU/jgDNuJkAJeIIHFTdLkPi9x9b14RZgaOa1EJ2enNx7MkN/MTCXw/fyZn9njOQHP jHSu4mWS4tv0xdmCGbJSiSGtYelgqrMmfJuTQHXRCsDIDSL8FAqCSxn+vXNP8wbwEar8 2A2kAUcrkKlsf0PVKN5tVPywaQ8hPiMwMMdIs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6WeZp2xSEO9KMoHBSdNPIoAis3aVnYcTFVvYqbzv6U4=; b=J1cnSY8TjxovoP31zkw0jIpYYWFWIm6xixBoiDDr7Ip7q1+JQWGacCL8TPTMcUqIb2 f5v8nZXEQYsgFwHTLG8KlrZyYaPdme77wkjwXXZ4G8E0QE+XoOPyRJFkV9/KxRXuMJfe a6lScz6xLs4G3K+B2TwaSSR6LtUEytaVU9dyCc+sFD0t1bWtCTtvHdpf2JMKBo7SqW6C VXrIc7Nw4DbXjir+WHPphxdSx5t193IW47siE3w/FMe3Eml6zXQvlKZ4knPUsL82ZKjI FdfgC0Pb7jzD0nJxws9EHohei1DT9N/VHlmCjGukgh6AnlQtvn3Met7oId1V9N1M9NGE WhnQ== X-Gm-Message-State: AA6/9Rm3+nUTrw1IbGEdYuIWoTKPBzOnxISmF+WRTQCUDAuNjRh/IuGAcZOSLUlSMnfGawYh X-Received: by 10.25.138.215 with SMTP id m206mr5326248lfd.30.1476883700865; Wed, 19 Oct 2016 06:28:20 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id z204sm3663405lfa.11.2016.10.19.06.28.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 19 Oct 2016 06:28:19 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [RESEND/PATCH v6 1/3] clk: qcom: Add A53 PLL support Date: Wed, 19 Oct 2016 16:28:14 +0300 Message-Id: <20161019132816.31073-2-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161019132816.31073-1-georgi.djakov@linaro.org> References: <20161019132816.31073-1-georgi.djakov@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the PLL, which generates the higher range of CPU frequencies on MSM8916 platforms. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,a53-pll.txt | 17 ++++ drivers/clk/qcom/Kconfig | 9 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53-pll.c | 94 ++++++++++++++++++++++ 4 files changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53-pll.txt create mode 100644 drivers/clk/qcom/a53-pll.c -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/qcom,a53-pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53-pll.txt new file mode 100644 index 000000000000..50e71e4e13a6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53-pll.txt @@ -0,0 +1,17 @@ +A53 PLL Binding +--------------- +The A53 PLL is the main CPU PLL used for frequencies above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,a53-pll" + +- reg : shall contain base register location and length + +Example: + + a53pll: a53pll@0b016000 { + compatible = "qcom,a53-pll"; + reg = <0x0b016000 0x40>; + }; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0146d3c2547f..a889f0b14b54 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -150,3 +150,12 @@ config MSM_MMCC_8996 Support for the multimedia clock controller on msm8996 devices. Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. + +config QCOM_A53PLL + bool "A53 PLL" + depends on COMMON_CLK_QCOM + help + Support for the A53 PLL on some Qualcomm devices. It provides + support for CPU frequencies above 1GHz. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8916. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1fb1f5476cb0..7d27f47f0c92 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c new file mode 100644 index 000000000000..43902080f34b --- /dev/null +++ b/drivers/clk/qcom/a53-pll.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2016, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "clk-pll.h" +#include "clk-regmap.h" + +static struct pll_freq_tbl a53pll_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1094400000, 57, 0x0, 0x1, 0 }, + { 1152000000, 62, 0x0, 0x1, 0 }, + { 1209600000, 65, 0x0, 0x1, 0 }, + { 1401600000, 73, 0x0, 0x1, 0 }, +}; + +static const struct regmap_config a53pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40, + .fast_io = true, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; + +static const struct of_device_id qcom_a53pll_match_table[] = { + { .compatible = "qcom,a53-pll" }, + { } +}; + +static int qcom_a53pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct clk_pll *pll; + struct resource *res; + void __iomem *base; + struct regmap *regmap; + struct clk_init_data init; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pll->l_reg = 0x04, + pll->m_reg = 0x08, + pll->n_reg = 0x0c, + pll->config_reg = 0x14, + pll->mode_reg = 0x00, + pll->status_reg = 0x1c, + pll->status_bit = 16, + pll->freq_tbl = a53pll_freq, + + init.name = node->name; + init.parent_names = (const char *[]){ "xo" }, + init.num_parents = 1, + init.ops = &clk_pll_sr2_ops, + init.flags = CLK_IS_CRITICAL; + pll->clkr.hw.init = &init; + + return devm_clk_register_regmap(dev, &pll->clkr); +} + +static struct platform_driver qcom_a53pll_driver = { + .probe = qcom_a53pll_probe, + .driver = { + .name = "qcom-a53pll", + .of_match_table = qcom_a53pll_match_table, + }, +}; + +builtin_platform_driver(qcom_a53pll_driver);