From patchwork Thu Dec 15 02:11:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9475421 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A3D9160825 for ; Thu, 15 Dec 2016 02:12:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B217286B2 for ; Thu, 15 Dec 2016 02:12:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8FF61286EB; Thu, 15 Dec 2016 02:12:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 694C7286B2 for ; Thu, 15 Dec 2016 02:12:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753230AbcLOCMJ (ORCPT ); Wed, 14 Dec 2016 21:12:09 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:26656 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752366AbcLOCMJ (ORCPT ); Wed, 14 Dec 2016 21:12:09 -0500 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie3.idc.renesas.com with ESMTP; 15 Dec 2016 11:12:07 +0900 Received: from relmlac2.idc.renesas.com (relmlac2.idc.renesas.com [10.200.69.22]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 19AD65ECC9; Thu, 15 Dec 2016 11:12:07 +0900 (JST) Received: by relmlac2.idc.renesas.com (Postfix, from userid 0) id 17AD828070; Thu, 15 Dec 2016 11:12:07 +0900 (JST) Received: from relmlac2.idc.renesas.com (localhost [127.0.0.1]) by relmlac2.idc.renesas.com (Postfix) with ESMTP id 1064B2806F; Thu, 15 Dec 2016 11:12:07 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac2.idc.renesas.com with ESMTP id MAD17747; Thu, 15 Dec 2016 11:12:07 +0900 X-IronPort-AV: E=Sophos;i="5.33,349,1477926000"; d="scan'208";a="228704910" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 15 Dec 2016 11:12:05 +0900 Received: from localhost.localdomain (unknown [143.103.58.181]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 96F7826A; Thu, 15 Dec 2016 02:12:00 +0000 (UTC) From: Chris Brandt To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Simon Horman , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Brandt Subject: [PATCH] clk: renesas: mstp: Support 8-bit registers for r7s72100 Date: Wed, 14 Dec 2016 21:11:34 -0500 Message-Id: <20161215021134.14902-1-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The RZ/A1 is different than the other Renesas SOCs because the MSTP registers are 8-bit instead of 32-bit and if you try writing values as 32-bit nothing happens...meaning this driver never worked for r7s72100. Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt --- drivers/clk/renesas/clk-mstp.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c index 9375777..69c3604 100644 --- a/drivers/clk/renesas/clk-mstp.c +++ b/drivers/clk/renesas/clk-mstp.c @@ -59,6 +59,21 @@ struct mstp_clock { #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) +/** + * Some devices only have 8-bit registers + */ +bool reg_width_8bit; + +static inline u32 cpg_mstp_read(u32 __iomem *reg) +{ + return reg_width_8bit ? readb(reg) : clk_readl(reg); +} + +static inline void cpg_mstp_write(u32 val, u32 __iomem *reg) +{ + reg_width_8bit ? writeb(val, reg) : clk_writel(val, reg); +} + static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) { struct mstp_clock *clock = to_mstp_clock(hw); @@ -70,12 +85,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) spin_lock_irqsave(&group->lock, flags); - value = clk_readl(group->smstpcr); + value = cpg_mstp_read(group->smstpcr); if (enable) value &= ~bitmask; else value |= bitmask; - clk_writel(value, group->smstpcr); + cpg_mstp_write(value, group->smstpcr); spin_unlock_irqrestore(&group->lock, flags); @@ -83,7 +98,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) return 0; for (i = 1000; i > 0; --i) { - if (!(clk_readl(group->mstpsr) & bitmask)) + if (!(cpg_mstp_read(group->mstpsr) & bitmask)) break; cpu_relax(); } @@ -114,9 +129,9 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) u32 value; if (group->mstpsr) - value = clk_readl(group->mstpsr); + value = cpg_mstp_read(group->mstpsr); else - value = clk_readl(group->smstpcr); + value = cpg_mstp_read(group->smstpcr); return !(value & BIT(clock->bit_index)); } @@ -243,6 +258,14 @@ static void __init cpg_mstp_clocks_init(struct device_node *np) } CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init); +static void __init cpg_mstp_clocks_init8(struct device_node *np) +{ + reg_width_8bit = true; + cpg_mstp_clocks_init(np); +} +CLK_OF_DECLARE(cpg_mstp_clks8, "renesas,r7s72100-mstp-clocks", + cpg_mstp_clocks_init8); + int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev) { struct device_node *np = dev->of_node;