From patchwork Tue Jan 24 02:32:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 9533953 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 373E16046A for ; Tue, 24 Jan 2017 02:39:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 28FEF205D6 for ; Tue, 24 Jan 2017 02:39:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1DBB82094F; Tue, 24 Jan 2017 02:39:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2D32205D6 for ; Tue, 24 Jan 2017 02:39:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751011AbdAXCjV (ORCPT ); Mon, 23 Jan 2017 21:39:21 -0500 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:44718 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751014AbdAXCjU (ORCPT ); Mon, 23 Jan 2017 21:39:20 -0500 Received: by wens.csie.org (Postfix, from userid 1000) id D8A2B5FC85; Tue, 24 Jan 2017 10:32:32 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio Date: Tue, 24 Jan 2017 10:32:27 +0800 Message-Id: <20170124023230.3990-9-wens@csie.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170124023230.3990-1-wens@csie.org> References: <20170124023230.3990-1-wens@csie.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We are moving towards handling GPIO pinmux settings that don't require extra bias or drive strength settings to use the GPIO bindings only. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 10 ---------- drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 24 ++++++++++++------------ 2 files changed, 12 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts index 3ab5c0c09d93..b6958e8f2f01 100644 --- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts +++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts @@ -50,7 +50,6 @@ }; &codec { - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ allwinner,audio-routing = "Headphone", "HP", @@ -62,12 +61,3 @@ "Headset Mic", "HBIAS"; status = "okay"; }; - -&pio { - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c index 5626e4674f48..e13e313ce4f5 100644 --- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c @@ -42,7 +42,7 @@ static struct clk_div_table pll_cpux_p_div_table[] = { static struct ccu_nm pll_c0cpux_clk = { .enable = BIT(31), .lock = BIT(0), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table), .common = { .reg = 0x000, @@ -56,7 +56,7 @@ static struct ccu_nm pll_c0cpux_clk = { static struct ccu_nm pll_c1cpux_clk = { .enable = BIT(31), .lock = BIT(1), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table), .common = { .reg = 0x004, @@ -78,7 +78,7 @@ static struct ccu_nm pll_c1cpux_clk = { static struct ccu_nm pll_audio_clk = { .enable = BIT(31), .lock = BIT(2), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0), .common = { .reg = 0x008, @@ -93,7 +93,7 @@ static struct ccu_nm pll_audio_clk = { static struct ccu_nkmp pll_periph0_clk = { .enable = BIT(31), .lock = BIT(3), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -109,7 +109,7 @@ static struct ccu_nkmp pll_periph0_clk = { static struct ccu_nkmp pll_ve_clk = { .enable = BIT(31), .lock = BIT(4), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -125,7 +125,7 @@ static struct ccu_nkmp pll_ve_clk = { static struct ccu_nkmp pll_ddr_clk = { .enable = BIT(31), .lock = BIT(5), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -141,7 +141,7 @@ static struct ccu_nkmp pll_ddr_clk = { static struct ccu_nm pll_video0_clk = { .enable = BIT(31), .lock = BIT(6), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .common = { .reg = 0x018, @@ -156,7 +156,7 @@ static struct ccu_nm pll_video0_clk = { static struct ccu_nkmp pll_video1_clk = { .enable = BIT(31), .lock = BIT(7), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */ .common = { @@ -172,7 +172,7 @@ static struct ccu_nkmp pll_video1_clk = { static struct ccu_nkmp pll_gpu_clk = { .enable = BIT(31), .lock = BIT(8), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -188,7 +188,7 @@ static struct ccu_nkmp pll_gpu_clk = { static struct ccu_nkmp pll_de_clk = { .enable = BIT(31), .lock = BIT(9), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -204,7 +204,7 @@ static struct ccu_nkmp pll_de_clk = { static struct ccu_nkmp pll_isp_clk = { .enable = BIT(31), .lock = BIT(10), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -220,7 +220,7 @@ static struct ccu_nkmp pll_isp_clk = { static struct ccu_nkmp pll_periph1_clk = { .enable = BIT(31), .lock = BIT(11), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = {