From patchwork Tue Feb 7 20:28:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 9561113 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B9E1660547 for ; Tue, 7 Feb 2017 20:29:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ABB2A2521E for ; Tue, 7 Feb 2017 20:29:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9FCA728173; Tue, 7 Feb 2017 20:29:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 091832521E for ; Tue, 7 Feb 2017 20:29:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932270AbdBGU3X (ORCPT ); Tue, 7 Feb 2017 15:29:23 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:45888 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755528AbdBGU23 (ORCPT ); Tue, 7 Feb 2017 15:28:29 -0500 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id C1EFC886C4; Wed, 8 Feb 2017 09:28:25 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1486499305; bh=2MV/v4bB+PwoMf4nqniy0uu7VWl5f8T6nAz5xRV8sKU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=VxyCTKDJR8yn5zr2mTKath43ofyZfe6mfZ0zc0uUlGF/NkCTVrnzlP4WZBJlatfSQ B9LGY5Xg11umDKmN6qsJYSPEvhzqkGiwZZS2DTxiEPSJQcvXds8tkDIHpIPWl+ijBd 1GXo0/Oyd01aO6H/rohfwhLjeQIhZvinmAODejMU= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 7, 9061) id ; Wed, 08 Feb 2017 09:28:25 +1300 Received: from chrisp-dl.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 382CD13EFE2; Wed, 8 Feb 2017 09:28:25 +1300 (NZDT) Received: by chrisp-dl.atlnz.lc (Postfix, from userid 1030) id 5E26F1E1D6A; Wed, 8 Feb 2017 09:28:25 +1300 (NZDT) From: Chris Packham To: linux-arm-kernel@lists.infradead.org Cc: Chris Packham , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Russell King , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] ARM: dts: mvebu: Move mv98dx3236 clock bindings Date: Wed, 8 Feb 2017 09:28:14 +1300 Message-Id: <20170207202815.20226-6-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.11.0.24.ge6920cf In-Reply-To: <20170207202815.20226-1-chris.packham@alliedtelesis.co.nz> References: <20170207202815.20226-1-chris.packham@alliedtelesis.co.nz> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This moves the coreclk binding for the 98dx3236 SoC to the DFX block where the sampled at reset register is located and switches to using the correct gating clock compatible string. Signed-off-by: Chris Packham --- Notes: Changes in v2: - New. Split out from "clk: mvebu: Expand mv98dx3236-core-clock support" .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 +++++++ .../devicetree/bindings/clock/mvebu-gated-clock.txt | 11 +++++++++++ arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 +++++++------- 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt index eb985a633d59..796c260c183d 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt @@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x: 4 = dclk (SDRAM Interface Clock) 5 = refclk (Reference Clock) +The following is a list of provided IDs and clock names on 98dx3236: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = ddrclk (DDR clock) + 3 = mpll (MPLL Clock) + The following is a list of provided IDs and clock names on Kirkwood and Dove: 0 = tclk (Internal Bus clock) 1 = cpuclk (CPU0 clock) @@ -49,6 +55,7 @@ Required properties: "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks + "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks "marvell,dove-core-clock" - for Dove SoC core clocks "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt index 5142efc8099d..de562da2ae77 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt @@ -119,6 +119,16 @@ ID Clock Peripheral 29 sata1lnk 30 sata1 SATA Host 1 +The following is a list of provided IDs for 98dx3236: +ID Clock Peripheral +----------------------------------- +3 ge1 Gigabit Ethernet 1 +4 ge0 Gigabit Ethernet 0 +5 pex0 PCIe Cntrl 0 +17 sdio SDHCI Host +18 usb0 USB Host 0 +22 xor0 XOR DMA 0 + The following is a list of provided IDs for Dove: ID Clock Peripheral ----------------------------------- @@ -169,6 +179,7 @@ Required properties: "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating + "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating "marvell,dove-gating-clock" - for Dove SoC clock gating "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating - reg : shall be the register address of the Clock Gating Control register diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index e4baa97836e7..e80a5ee835e5 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -176,18 +176,12 @@ }; gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-xp-gating-clock"; + compatible = "marvell,mv98dx3236-gating-clock"; reg = <0x18220 0x4>; clocks = <&coreclk 0>; #clock-cells = <1>; }; - coreclk: mvebu-sar@18230 { - compatible = "marvell,mv98dx3236-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,mv98dx3236-cpu-clock"; @@ -264,6 +258,12 @@ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; reg = ; + coreclk: mvebu-sar@f8204 { + compatible = "marvell,mv98dx3236-core-clock"; + reg = <0xf8204 0x4>; + #clock-cells = <1>; + }; + soc-id@f8244 { compatible = "marvell,mv98dx3236-soc-id"; reg = <0xf8244 0x4>;