From patchwork Tue Feb 14 16:08:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9572169 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7286D6045F for ; Tue, 14 Feb 2017 16:08:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B2E628428 for ; Tue, 14 Feb 2017 16:08:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4E44D2842C; Tue, 14 Feb 2017 16:08:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 21EFE28428 for ; Tue, 14 Feb 2017 16:08:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754439AbdBNQIb (ORCPT ); Tue, 14 Feb 2017 11:08:31 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:62280 "EHLO relmlie4.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754098AbdBNQIb (ORCPT ); Tue, 14 Feb 2017 11:08:31 -0500 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie4.idc.renesas.com with ESMTP; 15 Feb 2017 01:08:28 +0900 Received: from relmlac2.idc.renesas.com (relmlac2.idc.renesas.com [10.200.69.22]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id 0D48A3D032; Wed, 15 Feb 2017 01:08:28 +0900 (JST) Received: by relmlac2.idc.renesas.com (Postfix, from userid 0) id 053B228076; Wed, 15 Feb 2017 01:08:27 +0900 (JST) Received: from relmlac2.idc.renesas.com (localhost [127.0.0.1]) by relmlac2.idc.renesas.com (Postfix) with ESMTP id F346D28070; Wed, 15 Feb 2017 01:08:27 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac2.idc.renesas.com with ESMTP id BAZ03201; Wed, 15 Feb 2017 01:08:27 +0900 X-IronPort-AV: E=Sophos;i="5.35,161,1483974000"; d="scan'208";a="234534134" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 15 Feb 2017 01:08:26 +0900 Received: from localhost.localdomain (unknown [172.27.49.108]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 5AF11307; Tue, 14 Feb 2017 16:08:21 +0000 (UTC) From: Chris Brandt To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Simon Horman , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH v3] clk: renesas: mstp: ensure register writes complete Date: Tue, 14 Feb 2017 11:08:05 -0500 Message-Id: <20170214160805.20156-1-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When there is no status bit, it is possible for the clock enable/disable operation to have not completed by the time the driver code resumes execution. This is due to the fact that write operations are sometimes queued and delayed internally. Doing a read ensures the write operations has completed. Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v3: * changed clk_readl to cpg_mstp_read to take into account 8-bit registers * added Reviewed by Geert Uytterhoeven v2: * added Fixes because technically this is a bug fix --- drivers/clk/renesas/clk-mstp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c index 3ce819c..4067216 100644 --- a/drivers/clk/renesas/clk-mstp.c +++ b/drivers/clk/renesas/clk-mstp.c @@ -91,6 +91,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) value |= bitmask; cpg_mstp_write(group, value, group->smstpcr); + if (!group->mstpsr) { + /* dummy read to ensure write has completed */ + cpg_mstp_read(group, group->smstpcr); + barrier_data(group->smstpcr); + } + spin_unlock_irqrestore(&group->lock, flags); if (!enable || !group->mstpsr)