From patchwork Wed Feb 22 15:03:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 9586957 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B80DF60578 for ; Wed, 22 Feb 2017 15:04:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A0A5C2862B for ; Wed, 22 Feb 2017 15:04:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95A652864D; Wed, 22 Feb 2017 15:04:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A7C992863E for ; Wed, 22 Feb 2017 15:04:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932703AbdBVPEJ (ORCPT ); Wed, 22 Feb 2017 10:04:09 -0500 Received: from webbox1416.server-home.net ([77.236.96.61]:52287 "EHLO webbox1416.server-home.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932754AbdBVPEI (ORCPT ); Wed, 22 Feb 2017 10:04:08 -0500 Received: from imapserver.systec-electronic.com (unknown [212.185.67.146]) by webbox1416.server-home.net (Postfix) with ESMTPA id D3DA427A4D1; Wed, 22 Feb 2017 16:04:06 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by imapserver.systec-electronic.com (Postfix) with ESMTP id CEAE1DA0A3F; Wed, 22 Feb 2017 16:04:06 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at imapserver.systec-electronic.com Received: from imapserver.systec-electronic.com ([127.0.0.1]) by localhost (imapserver.systec-electronic.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id W8lAQ9zGDe5a; Wed, 22 Feb 2017 16:04:03 +0100 (CET) Received: from localhost.localdomain (ws-stein.systec.local [192.168.10.116]) by imapserver.systec-electronic.com (Postfix) with ESMTP id C3696DA0A55; Wed, 22 Feb 2017 16:04:03 +0100 (CET) From: Alexander Stein To: Michael Turquette , Stephen Boyd Cc: Alexander Stein , linux-clk@vger.kernel.org Subject: [PATCH 1/3] clk: ls1021a: new platform clock driver Date: Wed, 22 Feb 2017 16:03:47 +0100 Message-Id: <20170222150349.16790-2-alexander.stein@systec-electronic.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170222150349.16790-1-alexander.stein@systec-electronic.com> References: <20170222150349.16790-1-alexander.stein@systec-electronic.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This driver currently only implements the QSPI divider register SCFG_QSPI_CFG. Signed-off-by: Alexander Stein --- drivers/clk/Makefile | 1 + drivers/clk/clk-ls1021a.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 drivers/clk/clk-ls1021a.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 925081e..611f53f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o +obj-$(CONFIG_SOC_LS1021A) += clk-ls1021a.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o diff --git a/drivers/clk/clk-ls1021a.c b/drivers/clk/clk-ls1021a.c new file mode 100644 index 0000000..2f64806 --- /dev/null +++ b/drivers/clk/clk-ls1021a.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017 SYS TEC electronic GmbH + * Alexander Stein + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include +#include +#include + +static const struct clk_div_table qspi_cfg_div_table[] = { + { 0x0, 256 }, { 0x1, 64 }, { 0x2, 32 }, { 0x3, 24 }, + { 0x4, 20 }, { 0x5, 15 }, { 0x6, 12 }, { 0x7, 8 }, + { 0 }, +}; + +static void __init scfg_qspi_cfg_ls1021a_init(struct device_node *np) +{ + const char *parent_name; + const char *name; + void __iomem *base; + struct clk *parent_clk; + struct clk *clk; + struct resource res; + + base = of_iomap(np, 0); + if (!base) { + pr_warn("Failed to map address range for node %s\n", np->name); + return; + } + + parent_clk = of_clk_get(np, 0); + if (IS_ERR(parent_clk)) { + pr_warn("Failed to get clock for node %s\n", np->name); + return; + } + + /* Register the input clock under the desired name. */ + parent_name = __clk_get_name(parent_clk); + + if (of_property_read_string(np, "clock-output-names", &name)) + name = np->name; + + /* Works only as those 4 bits (Bits 28-31 big endian) do not cross byte boundary */ + clk = clk_register_divider_table(NULL, name, parent_name, + 0, base, + 4, 4, 0, qspi_cfg_div_table, NULL); + if (IS_ERR(clk)) { + pr_warn("Failed to register divider table clock (%ld)\n", PTR_ERR(clk)); + return; + } + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(scfg_qspi_cfg_ls1021a, "fsl,scfg-qspi-cfg-ls1021a", scfg_qspi_cfg_ls1021a_init);