From patchwork Wed May 3 03:09:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 9708735 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4D2E160351 for ; Wed, 3 May 2017 03:09:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3D18528557 for ; Wed, 3 May 2017 03:09:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 31BE8285E2; Wed, 3 May 2017 03:09:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 44AA828557 for ; Wed, 3 May 2017 03:09:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751382AbdECDJe (ORCPT ); Tue, 2 May 2017 23:09:34 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:43312 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751329AbdECDJd (ORCPT ); Tue, 2 May 2017 23:09:33 -0400 Received: by wens.csie.org (Postfix, from userid 1000) id 7172B5FE51; Wed, 3 May 2017 11:09:30 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v2 2/8] clk: Provide option to query hardware for clk phase Date: Wed, 3 May 2017 11:09:23 +0800 Message-Id: <20170503030929.28763-3-wens@csie.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170503030929.28763-1-wens@csie.org> References: <20170503030929.28763-1-wens@csie.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On some hardware, the clk phase is tied to the parent clk's rate and some clk delay programmed into the hardware. As the parent clk rate changes, so does the clk phase. Add a clk flag specifying not to use the cached clk phase, but always query the hardware for it. Signed-off-by: Chen-Yu Tsai --- drivers/clk/clk.c | 6 +++++- include/linux/clk-provider.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 67201f67a14a..05e2481c1340 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1929,7 +1929,11 @@ static int clk_core_get_phase(struct clk_core *core) int ret; clk_prepare_lock(); - ret = core->phase; + if (core && (core->flags & CLK_GET_PHASE_NOCACHE) && + core->ops->get_phase) + ret = core->ops->get_phase(core->hw); + else + ret = core->phase; clk_prepare_unlock(); return ret; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index a428aec36ace..e2e856b1a81f 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -35,6 +35,7 @@ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) +#define CLK_GET_PHASE_NOCACHE BIT(13) /* do not use the cached clk phase */ struct clk; struct clk_hw;