| Message ID | 20170504135006.16483-3-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Thu, May 04, 2017 at 10:07:47PM +0800, Icenowy Zheng wrote: > > > 于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard <maxime.ripard@free-electrons.com> 写到: > >On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote: > >> Allwinner A10, A20 and R40 SoCs have similar GPIO layout. > >> > >> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support > >> into A10 driver, and add R40 support into it. > > > >While your commit log is good, the commit title is misleading since > >you're not adding it to the A10 driver. You just adding SoC IDs > >definitions > > Is "pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs" OK? Yep, it is, thanks! Maxime
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index a9d315a1256c..1bfc0d8a55df 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -87,6 +87,9 @@ #define PINCTRL_SUN5I_GR8 BIT(3) #define PINCTRL_SUN6I_A31 BIT(4) #define PINCTRL_SUN6I_A31S BIT(5) +#define PINCTRL_SUN4I_A10 BIT(6) +#define PINCTRL_SUN7I_A20 BIT(7) +#define PINCTRL_SUN8I_R40 BIT(8) struct sunxi_desc_function { unsigned long variant;
Allwinner A10, A20 and R40 SoCs have similar GPIO layout. Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support into A10 driver, and add R40 support into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++ 1 file changed, 3 insertions(+)