From patchwork Mon May 15 05:54:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 9726111 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 81ADE60380 for ; Mon, 15 May 2017 05:55:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71AC72894E for ; Mon, 15 May 2017 05:55:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6683C28954; Mon, 15 May 2017 05:55:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D13602894E for ; Mon, 15 May 2017 05:55:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759232AbdEOFzG (ORCPT ); Mon, 15 May 2017 01:55:06 -0400 Received: from mail-pf0-f177.google.com ([209.85.192.177]:35929 "EHLO mail-pf0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759118AbdEOFzC (ORCPT ); Mon, 15 May 2017 01:55:02 -0400 Received: by mail-pf0-f177.google.com with SMTP id m17so57321941pfg.3 for ; Sun, 14 May 2017 22:55:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gYZU0wC8nBk3KWhRSKnWsdgRPBZjUjtXhsbpUphMBPs=; b=AvtRUP/9+3NjgFpOKTjLXq9bY3pEm4sDYhwlDv0xGRdfRHmznKDDoAoXglpfLc6ypg FfvFRxT681zc2DQFXF6/cDFiLOPADhomvnT8KPhnDW2pthnKZ/bo+GtuY0b7Fil4KUjg vPnYLJ8rwC6k4NtiabR8dV7V3WkbZjERgiGlo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gYZU0wC8nBk3KWhRSKnWsdgRPBZjUjtXhsbpUphMBPs=; b=XLNvLkaDatLAT3qIYTncPcMF2Yh7bX+GIxq5saxZuzWM2czX2tIKVCpSlFYvyMToJA GV8NsAQ4NgYBGqjWAjP6POO0aR0LUzbjRzriiI1TfzHD7Z2knOynrOetcdJwiBwszQnr aPvBst1+6SbS+fpZ1e+EPmhzpF+VOBSua/uqXJyQtjqdLal2R8KkqDQE5QLSGMKWrJ/Y 4GPy1RbnhQ1OQQBxR+4N6puEv6AtR43oYBk2SPhg3eT2Woh1e0xZQ6Sjo15RjfBkZcZn WjvL4WbNtmBkINszeeaOfQbm+efHxwBnllqMYGT38LIE6DRYSS/gq8MYvSTHmR2Yu+RG UYIg== X-Gm-Message-State: AODbwcCWJtR5HWZ8oo3vNHelhjdUP7h5TD4IENLDSxI2dZiJYKhK2Jyg jx+eG/Gc2hPfUpWk X-Received: by 10.99.117.66 with SMTP id f2mr4480876pgn.58.1494827702197; Sun, 14 May 2017 22:55:02 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.87]) by smtp.gmail.com with ESMTPSA id t5sm17315105pgo.48.2017.05.14.22.54.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 14 May 2017 22:55:01 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, guodong.xu@linaro.org, chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/3] clk: hi3660: add clocks for video encoder and decoder Date: Mon, 15 May 2017 13:54:22 +0800 Message-Id: <20170515055423.1803-2-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170515055423.1803-1-guodong.xu@linaro.org> References: <20170515055423.1803-1-guodong.xu@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chen Jun This patch adds clocks for video encoder and decoder. Signed-off-by: Chen Jun Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi3660.c | 23 +++++++++++++++++++++++ include/dt-bindings/clock/hi3660-clock.h | 10 ++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 143ce0c..ffc765a 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -47,9 +47,12 @@ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, }, { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, }, { HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 }, + { HI3660_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", 1, 1, 0, }, }; static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { + { HI3660_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys", + CLK_SET_RATE_PARENT, 0x0, 0, 0, }, { HI3660_HCLK_GATE_SDIO0, "hclk_gate_sdio0", "clk_div_sysbus", CLK_SET_RATE_PARENT, 0x0, 21, 0, }, { HI3660_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus", @@ -120,6 +123,10 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { CLK_SET_RATE_PARENT, 0x20, 27, 0, }, { HI3660_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus", CLK_SET_RATE_PARENT, 0x30, 1, 0, }, + { HI3660_CLK_GATE_VENC, "clk_gate_venc", "clk_div_venc", + CLK_SET_RATE_PARENT, 0x30, 10, 0, }, + { HI3660_CLK_GATE_VDEC, "clk_gate_vdec", "clk_div_vdec", + CLK_SET_RATE_PARENT, 0x30, 11, 0, }, { HI3660_PCLK_GATE_DSS, "pclk_gate_dss", "clk_div_cfgbus", CLK_SET_RATE_PARENT, 0x30, 12, 0, }, { HI3660_ACLK_GATE_DSS, "aclk_gate_dss", "clk_gate_vivobus", @@ -171,6 +178,10 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = { CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0", CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, }, + { HI3660_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec", + CLK_SET_RATE_PARENT, 0xf0, 15, CLK_GATE_HIWORD_MASK, }, + { HI3660_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc", + CLK_SET_RATE_PARENT, 0xf4, 0, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_GATE_UFSPHY_GT, "clk_gate_ufsphy_gt", "clk_div_ufsperi", CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_ANDGT_MMC, "clk_andgt_mmc", "clk_mux_mmc_pll", @@ -239,6 +250,8 @@ static const char *const clk_mux_spi_p[] = {"clkin_sys", "clk_div_spi",}; static const char *const clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",}; +static const char *const +clk_mux_venc_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll3", "clk_ppll3",}; static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p, @@ -283,6 +296,12 @@ static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { { HI3660_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_pll_p, ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2, CLK_MUX_HIWORD_MASK, }, + { HI3660_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p, + ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2, + CLK_MUX_HIWORD_MASK, }, + { HI3660_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_pll0123_p, + ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2, + CLK_MUX_HIWORD_MASK, }, { HI3660_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_pll0123_p, ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2, CLK_MUX_HIWORD_MASK, }, @@ -318,6 +337,10 @@ static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = { CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi", CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3660_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc", + CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3660_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec", + CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_vivobus_andgt", CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m", diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h index 1c00b7f..2cf01b4 100644 --- a/include/dt-bindings/clock/hi3660-clock.h +++ b/include/dt-bindings/clock/hi3660-clock.h @@ -154,6 +154,16 @@ #define HI3660_CLK_DIV_UFSPERI 137 #define HI3660_CLK_DIV_AOMM 138 #define HI3660_CLK_DIV_IOPERI 139 +#define HI3660_VENC_VOLT_HOLD 140 +#define HI3660_PERI_VOLT_HOLD 141 +#define HI3660_CLK_GATE_VENC 142 +#define HI3660_CLK_GATE_VDEC 143 +#define HI3660_CLK_ANDGT_VENC 144 +#define HI3660_CLK_ANDGT_VDEC 145 +#define HI3660_CLK_MUX_VENC 146 +#define HI3660_CLK_MUX_VDEC 147 +#define HI3660_CLK_DIV_VENC 148 +#define HI3660_CLK_DIV_VDEC 149 /* clk in pmuctrl */ #define HI3660_GATE_ABB_192 0