From patchwork Mon May 15 05:54:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 9726107 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 396E560380 for ; Mon, 15 May 2017 05:55:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 28A612894E for ; Mon, 15 May 2017 05:55:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1D41C28953; Mon, 15 May 2017 05:55:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62AE92895B for ; Mon, 15 May 2017 05:55:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759103AbdEOFzJ (ORCPT ); Mon, 15 May 2017 01:55:09 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:35128 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759363AbdEOFzH (ORCPT ); Mon, 15 May 2017 01:55:07 -0400 Received: by mail-pg0-f44.google.com with SMTP id q125so35435916pgq.2 for ; Sun, 14 May 2017 22:55:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4FCBE8l0k4GVV0QK40T/3dwOs5p9c+YakAAbIFHRVe8=; b=VbRG6/1MyOHZGraKY81ZC3eDXA4Is0tmv9sjZ9BtGjCITCQ09cPsAIXsdBPJuTM8+w UslRvuGEIfdoExjcPav0YAUmeiSwDV54CK6pJXjSklArNbkyWJPsW3nBvAWJlC/0Abgm TmCHU6YwiDLKHbfgo74VzWBhlH9gX+T7brrBg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4FCBE8l0k4GVV0QK40T/3dwOs5p9c+YakAAbIFHRVe8=; b=rTOVx1SmH2ZA73wThVEDZGgeW9odtSDxrMR8hMEEscPXbMROJWvMF0FilPeon3KmZd KY0Jzitpp5pIP/YqLSI9lsM0lGN6nABJuiIVqjMhQMhzITqBSXVczQj5FUzN4P/CZL+h qfIjgd2vTGlwM6tiPQ9M26l9VOzguyasRbGWC6AD2IqqSmoHJvfDRfijuXtCZ1h8kaor lk5b7UXxbwmeL9kPmn71M4/T4f4Td6hB5F56Xv8B9zUxygGTK0MDQaIcDUNpmm6O361j QbVjiovqfelCCp8Y33Hz0yizrMl8DCus1rOrEKTLqgrUz7tq+DEjBSHrfMH5lhvUmhxI XDhA== X-Gm-Message-State: AODbwcBZpv8eI9mDaC0kIZpzTQksKyPfowHzmCOcTCDHaSBHVtddhWex FwBoz35Hs5E6U8u7 X-Received: by 10.98.144.143 with SMTP id q15mr4449493pfk.200.1494827706826; Sun, 14 May 2017 22:55:06 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.87]) by smtp.gmail.com with ESMTPSA id t5sm17315105pgo.48.2017.05.14.22.55.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 14 May 2017 22:55:06 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, guodong.xu@linaro.org, chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Zheng Shaobo Subject: [PATCH 3/3] clk: hi3660: Set PPLL2 to 2880M Date: Mon, 15 May 2017 13:54:23 +0800 Message-Id: <20170515055423.1803-3-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170515055423.1803-1-guodong.xu@linaro.org> References: <20170515055423.1803-1-guodong.xu@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Zhong Kaihua Set PPLL2 to 2880M. With this patch, we saw better compatibility on various 1080p HDMI monitors. Signed-off-by: Zhong Kaihua Signed-off-by: Zheng Shaobo --- drivers/clk/hisilicon/clk-hi3660.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index ffc765a..fd5ce7f 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -20,7 +20,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, }, { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, }, { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, }, - { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 960000000, }, + { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000, }, { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, }, { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, }, { HI3660_PCLK, "pclk", NULL, 0, 20000000, }, @@ -42,7 +42,7 @@ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, }, { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, }, { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, }, - { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 2, 0, }, + { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, }, { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, }, { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, }, { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },