From patchwork Mon May 15 17:18:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9727617 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7955460386 for ; Mon, 15 May 2017 17:18:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 615C7205F8 for ; Mon, 15 May 2017 17:18:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 563E528992; Mon, 15 May 2017 17:18:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C3C34205F8 for ; Mon, 15 May 2017 17:18:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760232AbdEORSs (ORCPT ); Mon, 15 May 2017 13:18:48 -0400 Received: from mail-qt0-f182.google.com ([209.85.216.182]:34954 "EHLO mail-qt0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758575AbdEORSr (ORCPT ); Mon, 15 May 2017 13:18:47 -0400 Received: by mail-qt0-f182.google.com with SMTP id v27so82594973qtg.2 for ; Mon, 15 May 2017 10:18:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=QY8wtwfn4fvCkNyZ+78Ej2sYmTnbAXrDnkqi1gBey2g=; b=XAA9+YUe3EecOdaauR2ckZ70W2++MzaU6UiZ7mXicQmkjMEvVDMZs3QU6IK4rVKffc tBYJUZJ3naDUV2Ylzyi0i0LPOl3GGxqZOm6rgZl3/cGs0n/exC5bFUjq84ghCFcGW5Ze jY2FEWxKhiu9Vfk3R1t0JbRuysR8z8pYr8w0I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=QY8wtwfn4fvCkNyZ+78Ej2sYmTnbAXrDnkqi1gBey2g=; b=ab7RGbn3vdBKOxBa1qZeMPUWhDPbg/siODD/HNVncQ4/3NJUqbMG4h2paCDq4pIPJ0 EthTzCKHoSjookF5e6+sjlh++2XjrxMA6CV3tguNDo/m9UdIjLYrsdmNZ9EBpYmTOP7M jSTfnOcN9ehTsQ8F023SU6F0RfYr3JquF3jYjUoakz66EEvLRiOiurFmy0qtbbuw5Lea lptVlFBQmj/MSNWPIN/gmtKbstybQohRl6U5n2NWapK3Nh3s64tVq1k3iVT+ZKL8RcHW MWkdi2nWVPtkdvEjN52V9mGDpFM7mVIYc+jsQ4fb+jtwmi1RQbEdjMyG0GVVqfiRHvvI f4YA== X-Gm-Message-State: AODbwcBiZJOY31KGovx05aeis3lROKtPmFDlJGISiI59tInZ3wE+h+NP mKiRWqXWKXv7o8LP X-Received: by 10.25.25.139 with SMTP id 133mr1290320lfz.33.1494868726244; Mon, 15 May 2017 10:18:46 -0700 (PDT) Received: from fabina.bredbandsbolaget.se (c-0e0be055.014-348-6c756e10.cust.bredbandsbolaget.se. [85.224.11.14]) by smtp.gmail.com with ESMTPSA id f88sm2300966lfk.63.2017.05.15.10.18.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 May 2017 10:18:45 -0700 (PDT) From: Linus Walleij To: Michael Turquette , Stephen Boyd , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org Cc: Janos Laube , Paulius Zaleckas , linux-arm-kernel@lists.infradead.org, Hans Ulli Kroll , Florian Fainelli , linux-clk@vger.kernel.org, Linus Walleij Subject: [PATCH 1/5 v3] dt-bindings: Augment Gemini for clocks, resets Date: Mon, 15 May 2017 19:18:39 +0200 Message-Id: <20170515171839.953-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This augments the platform bindings for the Gemini SoC to include the fact that the system controller also provides clock and reset lindes, and adds all the required include files. Cc: Rob Herring Signed-off-by: Linus Walleij Acked-by: Rob Herring --- ChangeLog v2->v3: - Essentially a new patch from the two old patches adding bindings to the reset and clock controller separately. Instead add it all into the system controller and use one single compatible. Rob: I need to merge this together in front of the device tree changes that sprinkle references to the headers all over the Gemini device trees, so if this sits good with you please ACK it. --- Documentation/devicetree/bindings/arm/gemini.txt | 24 +++++++++++++++- include/dt-bindings/clock/cortina,gemini-clock.h | 29 +++++++++++++++++++ include/dt-bindings/reset/cortina,gemini-reset.h | 36 ++++++++++++++++++++++++ 3 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/cortina,gemini-clock.h create mode 100644 include/dt-bindings/reset/cortina,gemini-reset.h diff --git a/Documentation/devicetree/bindings/arm/gemini.txt b/Documentation/devicetree/bindings/arm/gemini.txt index 0041eb031116..55bf7ce96c44 100644 --- a/Documentation/devicetree/bindings/arm/gemini.txt +++ b/Documentation/devicetree/bindings/arm/gemini.txt @@ -24,6 +24,19 @@ Required nodes: global control registers, with the compatible string "cortina,gemini-syscon", "syscon"; + Required properties on the syscon: + - reg: syscon register location and size. + - #clock-cells: should be set to <1> - the system controller is also a + clock provider. + - #reset-cells: should be set to <1> - the system controller is also a + reset line provider. + + The clock sources have shorthand defines in the include file: + + + The reset lines have shorthand defines in the include file: + + - timer: the soc bus node must have a timer node pointing to the SoC timer block, with the compatible string "cortina,gemini-timer" See: clocksource/cortina,gemini-timer.txt @@ -56,12 +69,15 @@ Example: syscon: syscon@40000000 { compatible = "cortina,gemini-syscon", "syscon"; reg = <0x40000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; }; uart0: serial@42000000 { compatible = "ns16550a"; reg = <0x42000000 0x100>; - clock-frequency = <48000000>; + resets = <&syscon GEMINI_RESET_UART>; + clocks = <&syscon GEMINI_CLK_UART>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; }; @@ -73,12 +89,18 @@ Example: interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ + resets = <&syscon GEMINI_RESET_TIMER>; + /* APB clock or RTC clock */ + clocks = <&syscon GEMINI_CLK_APB>, + <&syscon GEMINI_CLK_RTC>; + clock-names = "PCLK", "EXTCLK"; syscon = <&syscon>; }; intcon: interrupt-controller@48000000 { compatible = "cortina,gemini-interrupt-controller"; reg = <0x48000000 0x1000>; + resets = <&syscon GEMINI_RESET_INTCON0>; interrupt-controller; #interrupt-cells = <2>; }; diff --git a/include/dt-bindings/clock/cortina,gemini-clock.h b/include/dt-bindings/clock/cortina,gemini-clock.h new file mode 100644 index 000000000000..acf5cd550b0c --- /dev/null +++ b/include/dt-bindings/clock/cortina,gemini-clock.h @@ -0,0 +1,29 @@ +#ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H +#define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H + +/* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */ +#define GEMINI_NUM_CLKS 20 + +#define GEMINI_CLK_RTC 0 +#define GEMINI_CLK_AHB 1 +#define GEMINI_CLK_APB 2 +#define GEMINI_CLK_CPU 3 +#define GEMINI_CLK_PCI 4 +#define GEMINI_CLK_TVC 5 +#define GEMINI_CLK_UART 6 +#define GEMINI_CLK_GATES 7 +#define GEMINI_CLK_GATE_SECURITY 7 +#define GEMINI_CLK_GATE_GMAC0 8 +#define GEMINI_CLK_GATE_GMAC1 9 +#define GEMINI_CLK_GATE_SATA0 10 +#define GEMINI_CLK_GATE_SATA1 11 +#define GEMINI_CLK_GATE_USB0 12 +#define GEMINI_CLK_GATE_USB1 13 +#define GEMINI_CLK_GATE_IDE 14 +#define GEMINI_CLK_GATE_PCI 15 +#define GEMINI_CLK_GATE_DDR 16 +#define GEMINI_CLK_GATE_FLASH 17 +#define GEMINI_CLK_GATE_TVC 18 +#define GEMINI_CLK_GATE_BOOT 19 + +#endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */ diff --git a/include/dt-bindings/reset/cortina,gemini-reset.h b/include/dt-bindings/reset/cortina,gemini-reset.h new file mode 100644 index 000000000000..aebecae43721 --- /dev/null +++ b/include/dt-bindings/reset/cortina,gemini-reset.h @@ -0,0 +1,36 @@ +#ifndef _DT_BINDINGS_RESET_CORTINA_GEMINI_H +#define _DT_BINDINGS_RESET_CORTINA_GEMINI_H + +#define GEMINI_RESET_DRAM 0 +#define GEMINI_RESET_FLASH 1 +#define GEMINI_RESET_IDE 2 +#define GEMINI_RESET_RAID 3 +#define GEMINI_RESET_SECURITY 4 +#define GEMINI_RESET_GMAC0 5 +#define GEMINI_RESET_GMAC1 6 +#define GEMINI_RESET_PCI 7 +#define GEMINI_RESET_USB0 8 +#define GEMINI_RESET_USB1 9 +#define GEMINI_RESET_DMAC 10 +#define GEMINI_RESET_APB 11 +#define GEMINI_RESET_LPC 12 +#define GEMINI_RESET_LCD 13 +#define GEMINI_RESET_INTCON0 14 +#define GEMINI_RESET_INTCON1 15 +#define GEMINI_RESET_RTC 16 +#define GEMINI_RESET_TIMER 17 +#define GEMINI_RESET_UART 18 +#define GEMINI_RESET_SSP 19 +#define GEMINI_RESET_GPIO0 20 +#define GEMINI_RESET_GPIO1 21 +#define GEMINI_RESET_GPIO2 22 +#define GEMINI_RESET_WDOG 23 +#define GEMINI_RESET_EXTERN 24 +#define GEMINI_RESET_CIR 25 +#define GEMINI_RESET_SATA0 26 +#define GEMINI_RESET_SATA1 27 +#define GEMINI_RESET_TVE 28 +#define GEMINI_RESET_CPU1 30 +#define GEMINI_RESET_GLOBAL 31 + +#endif