From patchwork Wed May 17 16:43:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9731675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8116160230 for ; Wed, 17 May 2017 17:06:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B550228458 for ; Wed, 17 May 2017 17:06:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A9F5628777; Wed, 17 May 2017 17:06:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 96F7828458 for ; Wed, 17 May 2017 17:06:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754256AbdEQQq2 (ORCPT ); Wed, 17 May 2017 12:46:28 -0400 Received: from hermes.aosc.io ([199.195.250.187]:44636 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754567AbdEQQqU (ORCPT ); Wed, 17 May 2017 12:46:20 -0400 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 8DDC54DD28; Wed, 17 May 2017 16:46:13 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Rob Herring , Chen-Yu Tsai Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 10/11] ARM: sun8i: h3: add display engine pipeline for TVE Date: Thu, 18 May 2017 00:43:53 +0800 Message-Id: <20170517164354.16399-11-icenowy@aosc.io> In-Reply-To: <20170517164354.16399-1-icenowy@aosc.io> References: <20170517164354.16399-1-icenowy@aosc.io> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As we have already the support for the TV encoder on Allwinner H3, add the display engine pipeline device tree nodes to its DTSI file. The H5 pipeline has some differences and will be enabled later. The currently-unused mixer0 and tcon0 are also needed, for the completement of the pipeline. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3.dtsi | 189 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..20172ef92415 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -41,6 +41,8 @@ */ #include "sunxi-h3-h5.dtsi" +#include +#include / { cpus { @@ -72,6 +74,193 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-h3-display-engine"; + allwinner,pipelines = <&mixer0>, + <&mixer1>; + status = "disabled"; + }; + + soc { + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-a83t-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&ccu CLK_DE>; + assigned-clock-parents = <&ccu CLK_PLL_DE>; + assigned-clock-rates = <432000000>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-h3-de2-mixer0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + + mixer0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@1200000 { + compatible = "allwinner,sun8i-h3-de2-mixer1"; + reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer1_out_tcon1: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon1_in_mixer1>; + }; + + mixer1_out_tcon0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon0_in_mixer1>; + }; + }; + }; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-h3-tcon0"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch1"; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + + tcon0_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon0>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun8i-h3-tcon1"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON1>; + clock-names = "ahb"; + resets = <&ccu RST_BUS_TCON1>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_mixer1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer1_out_tcon1>; + }; + + tcon1_in_mixer0: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer0_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon1>; + }; + }; + }; + }; + + tve0: tv-encoder@1e00000 { + compatible = "allwinner,sun8i-h3-tv-encoder"; + reg = <0x01e00000 0x1000>; + clocks = <&ccu CLK_BUS_TVE>, <&ccu CLK_TVE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_TVE>; + status = "disabled"; + + assigned-clocks = <&ccu CLK_TVE>; + assigned-clock-parents = <&ccu CLK_PLL_DE>; + assigned-clock-rates = <216000000>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon1: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon1_out_tve0>; + }; + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = ,