From patchwork Sun Jun 18 01:58:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 9794643 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 811EF601A1 for ; Sun, 18 Jun 2017 02:03:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7155E28526 for ; Sun, 18 Jun 2017 02:03:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6480B28552; Sun, 18 Jun 2017 02:03:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DEA8328526 for ; Sun, 18 Jun 2017 02:03:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753216AbdFRCDl (ORCPT ); Sat, 17 Jun 2017 22:03:41 -0400 Received: from sci-ig2.spreadtrum.com ([222.66.158.135]:65375 "EHLO SHSQR01.spreadtrum.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1753206AbdFRCDk (ORCPT ); Sat, 17 Jun 2017 22:03:40 -0400 Received: from ig2.spreadtrum.com (shcas03.spreadtrum.com [10.0.1.207]) by SHSQR01.spreadtrum.com with ESMTP id v5I22I0M050452 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Sun, 18 Jun 2017 10:02:19 +0800 (CST) (envelope-from Chunyan.Zhang@spreadtrum.com) Received: from SHCAS01.spreadtrum.com (10.0.1.201) by SHMBX02.spreadtrum.com (10.0.1.204) with Microsoft SMTP Server (TLS) id 15.0.847.32; Sun, 18 Jun 2017 10:02:17 +0800 Received: from localhost (10.0.73.143) by SHCAS01.spreadtrum.com (10.0.1.250) with Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend Transport; Sun, 18 Jun 2017 10:02:17 +0800 From: Chunyan Zhang To: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland CC: , , , , Arnd Bergmann , Mark Brown , Xiaolong Zhang , Orson Zhai , Geng Ren , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V1 9/9] arm64: dts: add ccu for SC9860 Date: Sun, 18 Jun 2017 09:58:55 +0800 Message-ID: <20170618015855.27738-10-chunyan.zhang@spreadtrum.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170618015855.27738-1-chunyan.zhang@spreadtrum.com> References: <20170618015855.27738-1-chunyan.zhang@spreadtrum.com> MIME-Version: 1.0 X-MAIL: SHSQR01.spreadtrum.com v5I22I0M050452 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now we have clock driver, so add clock dt for SC9860 platform. This patch also removed "ext-26m" from whale2.dtsi since it is described in sc9860-ccu.dtsi. Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/sc9860-ccu.dtsi | 67 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/sprd/sc9860.dtsi | 2 + arch/arm64/boot/dts/sprd/whale2.dtsi | 8 ---- 3 files changed, 69 insertions(+), 8 deletions(-) create mode 100644 arch/arm64/boot/dts/sprd/sc9860-ccu.dtsi diff --git a/arch/arm64/boot/dts/sprd/sc9860-ccu.dtsi b/arch/arm64/boot/dts/sprd/sc9860-ccu.dtsi new file mode 100644 index 0000000..e15bf2d --- /dev/null +++ b/arch/arm64/boot/dts/sprd/sc9860-ccu.dtsi @@ -0,0 +1,67 @@ +/* + * Spreadtrum SC9860 SoC CCU + * + * Copyright (C) 2017, Spreadtrum Communications Inc. + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +&soc { + ext_26m: ext-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_32m_sine0: ext-32m-sine0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000000>; + clock-output-names = "ext-32m-sine0"; + }; + + ext_32m_sine1: ext-32m-sine1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000000>; + clock-output-names = "ext-32m-sine1"; + }; + + ext_rco_100m: ext-rco-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "ext-rco-100m"; + }; + + ext_32k: ext-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + ccu: clk { + compatible = "sprd,sc9860-ccu"; + #clock-cells = <1>; + reg = <0 0x20000000 0 0x400>, + <0 0x20210000 0 0x3000>, + <0 0x402b0000 0 0x4000>, + <0 0x402d0000 0 0x400>, + <0 0x402e0000 0 0x4000>, + <0 0x40400000 0 0x400>, + <0 0x40880000 0 0x400>, + <0 0x415e0000 0 0x400>, + <0 0x60200000 0 0x400>, + <0 0x61000000 0 0x400>, + <0 0x61100000 0 0x3000>, + <0 0x62000000 0 0x4000>, + <0 0x62100000 0 0x4000>, + <0 0x63000000 0 0x400>, + <0 0x63100000 0 0x3000>, + <0 0x70b00000 0 0x3000>; + clocks = <&ext_26m>, <&ext_rco_100m>, <&ext_32k>; + clock-names = "ext-26m", "ext-rco-100m", "ext-32k"; + }; +}; diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 7b7d8ce..10ff7c6 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -7,7 +7,9 @@ */ #include +#include #include "whale2.dtsi" +#include "sc9860-ccu.dtsi" / { cpus { diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 7c217c5..9d69b84 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -59,13 +59,5 @@ status = "disabled"; }; }; - - }; - - ext_26m: ext-26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "ext_26m"; }; };