From patchwork Sun Jun 18 01:58:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 9794639 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C82C66038E for ; Sun, 18 Jun 2017 02:03:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B9C8E28526 for ; Sun, 18 Jun 2017 02:03:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE80B28552; Sun, 18 Jun 2017 02:03:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 41DC728550 for ; Sun, 18 Jun 2017 02:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753161AbdFRCDS (ORCPT ); Sat, 17 Jun 2017 22:03:18 -0400 Received: from sci-ig2.spreadtrum.com ([222.66.158.135]:37855 "EHLO SHSQR01.spreadtrum.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1753158AbdFRCDQ (ORCPT ); Sat, 17 Jun 2017 22:03:16 -0400 Received: from ig2.spreadtrum.com (shcas01.spreadtrum.com [10.0.1.201]) by SHSQR01.spreadtrum.com with ESMTP id v5I21ln8050294 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Sun, 18 Jun 2017 10:01:47 +0800 (CST) (envelope-from Chunyan.Zhang@spreadtrum.com) Received: from SHCAS01.spreadtrum.com (10.0.1.201) by SHMBX02.spreadtrum.com (10.0.1.204) with Microsoft SMTP Server (TLS) id 15.0.847.32; Sun, 18 Jun 2017 10:01:45 +0800 Received: from localhost (10.0.73.143) by SHCAS01.spreadtrum.com (10.0.1.250) with Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend Transport; Sun, 18 Jun 2017 10:01:45 +0800 From: Chunyan Zhang To: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland CC: , , , , Arnd Bergmann , Mark Brown , Xiaolong Zhang , Orson Zhai , Geng Ren , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V1 2/9] clk: sprd: Add common infrastructure Date: Sun, 18 Jun 2017 09:58:48 +0800 Message-ID: <20170618015855.27738-3-chunyan.zhang@spreadtrum.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170618015855.27738-1-chunyan.zhang@spreadtrum.com> References: <20170618015855.27738-1-chunyan.zhang@spreadtrum.com> MIME-Version: 1.0 X-MAIL: SHSQR01.spreadtrum.com v5I21ln8050294 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added Spreadtrum's clock driver common structure and registration code. Signed-off-by: Chunyan Zhang --- drivers/clk/Makefile | 1 + drivers/clk/sprd/Makefile | 3 ++ drivers/clk/sprd/ccu_common.c | 78 +++++++++++++++++++++++++++++++++++++ drivers/clk/sprd/ccu_common.h | 90 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 172 insertions(+) create mode 100644 drivers/clk/sprd/Makefile create mode 100644 drivers/clk/sprd/ccu_common.c create mode 100644 drivers/clk/sprd/ccu_common.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c19983a..1d62721 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_ARCH_SIRF) += sirf/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ +obj-$(CONFIG_ARCH_SPRD) += sprd/ obj-$(CONFIG_ARCH_STI) += st/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/ diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile new file mode 100644 index 0000000..8f802b2 --- /dev/null +++ b/drivers/clk/sprd/Makefile @@ -0,0 +1,3 @@ +ifneq ($(CONFIG_OF),) +obj-y += ccu_common.o +endif diff --git a/drivers/clk/sprd/ccu_common.c b/drivers/clk/sprd/ccu_common.c new file mode 100644 index 0000000..911f4ba --- /dev/null +++ b/drivers/clk/sprd/ccu_common.c @@ -0,0 +1,78 @@ +/* + * Spreadtrum clock infrastructure + * + * Copyright (C) 2017 Spreadtrum, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include "ccu_common.h" + +static inline void __iomem *ccu_find_base(struct ccu_addr_map *maps, + unsigned int num, unsigned int reg) +{ + int i; + + for (i = 0; i < num; i++) + if ((reg & 0xffff0000) == maps[i].phy) + return maps[i].virt; + + return 0; +} + +int sprd_ccu_probe(struct device_node *node, struct ccu_addr_map *maps, + unsigned int count, const struct sprd_ccu_desc *desc) +{ + int i, ret = 0; + struct ccu_common *cclk; + struct clk_hw *hw; + + for (i = 0; i < desc->num_ccu_clks; i++) { + cclk = desc->ccu_clks[i]; + if (!cclk) + continue; + + cclk->base = ccu_find_base(maps, count, cclk->reg); + if (!cclk->base) { + pr_err("%s: No mapped address found for clock(0x%x)\n", + __func__, cclk->reg); + return -EINVAL; + } + cclk->reg = cclk->reg & 0xffff; + } + + for (i = 0; i < desc->hw_clks->num; i++) { + + hw = desc->hw_clks->hws[i]; + + if (!hw) + continue; + + ret = clk_hw_register(NULL, hw); + if (ret) { + pr_err("Couldn't register clock %d - %s\n", + i, hw->init->name); + goto err_clk_unreg; + } + } + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, + desc->hw_clks); + if (ret) { + pr_err("Failed to add clock provider.\n"); + goto err_clk_unreg; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + hw = desc->hw_clks->hws[i]; + if (!hw) + continue; + + clk_hw_unregister(hw); + } + + return ret; +} diff --git a/drivers/clk/sprd/ccu_common.h b/drivers/clk/sprd/ccu_common.h new file mode 100644 index 0000000..ff07772 --- /dev/null +++ b/drivers/clk/sprd/ccu_common.h @@ -0,0 +1,90 @@ +/* + * Spreadtrum clock infrastructure + * + * Copyright (C) 2017 Spreadtrum, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _CCU_COMMON_H_ +#define _CCU_COMMON_H_ + +#include + +struct device_node; + +#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ + (&(struct clk_init_data) { \ + .flags = _flags, \ + .name = _name, \ + .parent_names = NULL, \ + .num_parents = 0, \ + .ops = _ops, \ + }) + +#define CLK_HW_INIT(_name, _parent, _ops, _flags) \ + (&(struct clk_init_data) { \ + .flags = _flags, \ + .name = _name, \ + .parent_names = (const char *[]) { _parent }, \ + .num_parents = 1, \ + .ops = _ops, \ + }) + +#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ + (&(struct clk_init_data) { \ + .flags = _flags, \ + .name = _name, \ + .parent_names = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .ops = _ops, \ + }) + +#define CLK_FIXED_FACTOR(_struct, _name, _parent, \ + _div, _mult, _flags) \ + struct clk_fixed_factor _struct = { \ + .div = _div, \ + .mult = _mult, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &clk_fixed_factor_ops, \ + _flags), \ + } + +struct ccu_common { + void __iomem *base; + u32 reg; + spinlock_t *lock; + struct clk_hw hw; +}; + +struct ccu_addr_map { + phys_addr_t phy; + void __iomem *virt; +}; + +static inline u32 ccu_readl(struct ccu_common *common) +{ + return readl(common->base + common->reg); +} + +static inline void ccu_writel(u32 val, struct ccu_common *common) +{ + writel(val, common->base + common->reg); +} + +static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) +{ + return container_of(hw, struct ccu_common, hw); +} + +struct sprd_ccu_desc { + struct ccu_common **ccu_clks; + unsigned long num_ccu_clks; + struct clk_hw_onecell_data *hw_clks; +}; + +int sprd_ccu_probe(struct device_node *node, struct ccu_addr_map *maps, + unsigned int count, const struct sprd_ccu_desc *desc); + +#endif /* _CCU_COMMON_H_ */