From patchwork Sun Jun 18 01:58:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 9794637 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 804C7601A1 for ; Sun, 18 Jun 2017 02:03:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 72C2D28526 for ; Sun, 18 Jun 2017 02:03:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 661BB28554; Sun, 18 Jun 2017 02:03:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 046CD28526 for ; Sun, 18 Jun 2017 02:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753131AbdFRCDA (ORCPT ); Sat, 17 Jun 2017 22:03:00 -0400 Received: from sci-ig2.spreadtrum.com ([222.66.158.135]:31532 "EHLO SHSQR01.spreadtrum.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1753110AbdFRCCz (ORCPT ); Sat, 17 Jun 2017 22:02:55 -0400 Received: from ig2.spreadtrum.com (shcas02.spreadtrum.com [10.0.1.202]) by SHSQR01.spreadtrum.com with ESMTP id v5I228d9050410 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Sun, 18 Jun 2017 10:02:08 +0800 (CST) (envelope-from Chunyan.Zhang@spreadtrum.com) Received: from SHCAS01.spreadtrum.com (10.0.1.201) by SHMBX03.spreadtrum.com (10.0.1.208) with Microsoft SMTP Server (TLS) id 15.0.847.32; Sun, 18 Jun 2017 10:01:49 +0800 Received: from localhost (10.0.73.143) by SHCAS01.spreadtrum.com (10.0.1.250) with Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend Transport; Sun, 18 Jun 2017 10:01:49 +0800 From: Chunyan Zhang To: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland CC: , , , , Arnd Bergmann , Mark Brown , Xiaolong Zhang , Orson Zhai , Geng Ren , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V1 4/9] clk: sprd: add mux clock support Date: Sun, 18 Jun 2017 09:58:50 +0800 Message-ID: <20170618015855.27738-5-chunyan.zhang@spreadtrum.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170618015855.27738-1-chunyan.zhang@spreadtrum.com> References: <20170618015855.27738-1-chunyan.zhang@spreadtrum.com> MIME-Version: 1.0 X-MAIL: SHSQR01.spreadtrum.com v5I228d9050410 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is a feature that can also be found in sprd composite clocks, provide two helpers that can be reused later on. Original-by: Xiaolong Zhang Signed-off-by: Chunyan Zhang --- drivers/clk/sprd/Makefile | 2 +- drivers/clk/sprd/ccu_mux.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/sprd/ccu_mux.h | 63 +++++++++++++++++++++++++++++++++++ 3 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/sprd/ccu_mux.c create mode 100644 drivers/clk/sprd/ccu_mux.h diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile index 333e2b2..dc89790 100644 --- a/drivers/clk/sprd/Makefile +++ b/drivers/clk/sprd/Makefile @@ -1,3 +1,3 @@ ifneq ($(CONFIG_OF),) -obj-y += ccu_common.o ccu_gate.o +obj-y += ccu_common.o ccu_gate.o ccu_mux.o endif diff --git a/drivers/clk/sprd/ccu_mux.c b/drivers/clk/sprd/ccu_mux.c new file mode 100644 index 0000000..51c744e --- /dev/null +++ b/drivers/clk/sprd/ccu_mux.c @@ -0,0 +1,82 @@ +/* + * Spreadtrum multiplexer clock driver + * + * Copyright (C) 2017 Spreadtrum, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include "ccu_mux.h" + +DEFINE_SPINLOCK(mux_lock); + +u8 ccu_mux_helper_get_parent(struct ccu_common *common, + struct ccu_mux_internal *mux) +{ + u32 reg; + u8 parent; + int num_parents; + int i; + + reg = ccu_readl(common); + parent = reg >> mux->shift; + parent &= (1 << mux->width) - 1; + + if (mux->table) { + num_parents = clk_hw_get_num_parents(&common->hw); + + for (i = 0; i < num_parents; i++) + if (parent == mux->table[i] || + (i < (num_parents - 1) && parent > mux->table[i] && + parent < mux->table[i + 1])) + return i; + if (i == num_parents) + return i - 1; + } + + return parent; +} + +static u8 ccu_mux_get_parent(struct clk_hw *hw) +{ + struct ccu_mux *cm = hw_to_ccu_mux(hw); + + return ccu_mux_helper_get_parent(&cm->common, &cm->mux); +} + +int ccu_mux_helper_set_parent(struct ccu_common *common, + struct ccu_mux_internal *mux, + u8 index) +{ + unsigned long flags = 0; + u32 reg; + + if (mux->table) + index = mux->table[index]; + + spin_lock_irqsave(common->lock, flags); + + reg = ccu_readl(common); + reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift); + ccu_writel(reg | (index << mux->shift), common); + + spin_unlock_irqrestore(common->lock, flags); + + return 0; +} + +static int ccu_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_mux *cm = hw_to_ccu_mux(hw); + + return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index); +} + +const struct clk_ops ccu_mux_ops = { + .get_parent = ccu_mux_get_parent, + .set_parent = ccu_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, +}; diff --git a/drivers/clk/sprd/ccu_mux.h b/drivers/clk/sprd/ccu_mux.h new file mode 100644 index 0000000..f3e3fb4 --- /dev/null +++ b/drivers/clk/sprd/ccu_mux.h @@ -0,0 +1,63 @@ +/* + * Spreadtrum multiplexer clock driver + * + * Copyright (C) 2017 Spreadtrum, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _CCU_MUX_H_ +#define _CCU_MUX_H_ + +#include "ccu_common.h" + +struct ccu_mux_internal { + u8 shift; + u8 width; + const u8 *table; +}; + +struct ccu_mux { + struct ccu_mux_internal mux; + struct ccu_common common; +}; + +#define _SPRD_CCU_MUX(_shift, _width, _table) \ + { \ + .shift = _shift, \ + .width = _width, \ + .table = _table, \ + } + +#define SPRD_CCU_MUX(_struct, _name, _parents, _table, \ + _reg, _shift, _width, \ + _flags) \ + struct ccu_mux _struct = { \ + .mux = _SPRD_CCU_MUX(_shift, _width, _table), \ + .common = { \ + .reg = _reg, \ + .lock = &mux_lock, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_mux_ops,\ + _flags), \ + } \ + } + +static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_mux, common); +} + +extern const struct clk_ops ccu_mux_ops; +extern spinlock_t mux_lock; + +u8 ccu_mux_helper_get_parent(struct ccu_common *common, + struct ccu_mux_internal *mux); +int ccu_mux_helper_set_parent(struct ccu_common *common, + struct ccu_mux_internal *mux, + u8 index); + +#endif /* _CCU_MUX_H_ */