From patchwork Tue Jul 11 10:56:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 9834467 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 401C360325 for ; Tue, 11 Jul 2017 11:04:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30F8D2656B for ; Tue, 11 Jul 2017 11:04:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 24F6B2821F; Tue, 11 Jul 2017 11:04:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B249C2656B for ; Tue, 11 Jul 2017 11:04:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753223AbdGKLEV (ORCPT ); Tue, 11 Jul 2017 07:04:21 -0400 Received: from sci-ig2.spreadtrum.com ([222.66.158.135]:11294 "EHLO SHSQR01.spreadtrum.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1753378AbdGKLEU (ORCPT ); Tue, 11 Jul 2017 07:04:20 -0400 Received: from ig2.spreadtrum.com (shcas01.spreadtrum.com [10.0.1.201]) by SHSQR01.spreadtrum.com with ESMTP id v6BB0lkc059308 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Tue, 11 Jul 2017 19:00:47 +0800 (CST) (envelope-from Chunyan.Zhang@spreadtrum.com) Received: from SHCAS01.spreadtrum.com (10.0.1.201) by SHMBX04.spreadtrum.com (10.0.1.214) with Microsoft SMTP Server (TLS) id 15.0.847.32; Tue, 11 Jul 2017 19:00:46 +0800 Received: from localhost (10.0.73.143) by SHCAS01.spreadtrum.com (10.0.1.250) with Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend Transport; Tue, 11 Jul 2017 19:00:47 +0800 From: Chunyan Zhang To: Stephen Boyd , Michael Turquette , Rob Herring , Mark Rutland CC: , , , , Arnd Bergmann , Mark Brown , Xiaolong Zhang , Ben Li , Orson Zhai , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V2 02/10] dt-bindings: Add Spreadtrum clock binding documentation Date: Tue, 11 Jul 2017 18:56:19 +0800 Message-ID: <20170711105627.20526-3-chunyan.zhang@spreadtrum.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170711105627.20526-1-chunyan.zhang@spreadtrum.com> References: <20170711105627.20526-1-chunyan.zhang@spreadtrum.com> MIME-Version: 1.0 X-MAIL: SHSQR01.spreadtrum.com v6BB0lkc059308 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce a new binding with its documentation for Spreadtrum clock sub-framework. Signed-off-by: Chunyan Zhang Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/sprd.txt | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt new file mode 100644 index 0000000..c6f3abf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd.txt @@ -0,0 +1,36 @@ +Spreadtrum Clock Binding +------------------------ + +Required properties: +- compatible: must contain the following compatible: + - "sprd,sc9860-clk" (only support SC9860 for the time being) + +- reg: Must contain the registers base address and length. + Clocks on most of Spreadtrum's SoCs were designed to locate in a few + different address areas, so there would be more than one items under + this property. + +- #clock-cells: must be 1 + +Example: + +clk: clk { + compatible = "sprd,sc9860-clk"; + #clock-cells = <1>; + reg = <0 0x20000000 0 0x400>, + <0 0x20210000 0 0x3000>, + <0 0x402b0000 0 0x4000>, + <0 0x402d0000 0 0x400>, + <0 0x402e0000 0 0x4000>, + <0 0x40400000 0 0x400>, + <0 0x40880000 0 0x400>, + <0 0x415e0000 0 0x400>, + <0 0x60200000 0 0x400>, + <0 0x61000000 0 0x400>, + <0 0x61100000 0 0x3000>, + <0 0x62000000 0 0x4000>, + <0 0x62100000 0 0x4000>, + <0 0x63000000 0 0x400>, + <0 0x63100000 0 0x3000>, + <0 0x70b00000 0 0x3000>; +};