From patchwork Fri Jul 14 06:42:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 9840015 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2208560393 for ; Fri, 14 Jul 2017 06:45:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 126C92877F for ; Fri, 14 Jul 2017 06:45:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0778D28777; Fri, 14 Jul 2017 06:45:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 88E8D28750 for ; Fri, 14 Jul 2017 06:45:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751367AbdGNGp3 (ORCPT ); Fri, 14 Jul 2017 02:45:29 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:58686 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751445AbdGNGnL (ORCPT ); Fri, 14 Jul 2017 02:43:11 -0400 Received: by wens.csie.org (Postfix, from userid 1000) id 112C65FE94; Fri, 14 Jul 2017 14:43:08 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Ulf Hansson , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 03/11] clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock Date: Fri, 14 Jul 2017 14:42:54 +0800 Message-Id: <20170714064302.20383-4-wens@csie.org> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20170714064302.20383-1-wens@csie.org> References: <20170714064302.20383-1-wens@csie.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The MMC2 clock supports a new timing mode. When the new mode is active, the output clock rate is halved. This patch sets the feature flag for the new timing mode, and adds a pre-divider based on the mode bit. Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 38 +++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index 947f9f6e05d2..ee6688e9b361 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -418,14 +418,36 @@ static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1", static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1", 0x08c, 8, 3, 0); -/* TODO Support MMC2 clock's new timing mode. */ -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, - 0x090, - 0, 4, /* M */ - 16, 2, /* P */ - 24, 2, /* mux */ - BIT(31), /* gate */ - 0); +/* + * MMC2 supports both old and new timing modes. When the new timing + * mode is active, the output clock rate is halved by two. Here we + * treat it as a variable pre-divider. Note that the pre-divider is + * _not_ included in the possible factors during a set clock rate + * operation. It is only read out. + */ +static const struct ccu_mux_var_prediv mmc2_new_timing_predivs[] = { + { .index = 0, .shift = 30, .width = 1 }, + { .index = 1, .shift = 30, .width = 1 }, +}; +static struct ccu_mp mmc2_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(0, 4), + .p = _SUNXI_CCU_DIV(16, 2), + .mux = { + .shift = 24, + .width = 2, + .var_predivs = mmc2_new_timing_predivs, + .n_var_predivs = ARRAY_SIZE(mmc2_new_timing_predivs), + }, + .common = { + .reg = 0x090, + .features = CCU_FEATURE_MMC_TIMING_SWITCH, + .hw.init = CLK_HW_INIT_PARENTS("mmc2", + mod0_default_parents, + &ccu_mp_ops, + CLK_GET_RATE_NOCACHE), + }, +}; static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2", 0x090, 20, 3, 0);