From patchwork Fri Jul 14 08:23:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 9840137 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 312EB60381 for ; Fri, 14 Jul 2017 08:24:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F81C27FB6 for ; Fri, 14 Jul 2017 08:24:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 120D22874B; Fri, 14 Jul 2017 08:24:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70A5327FB6 for ; Fri, 14 Jul 2017 08:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751166AbdGNIYB (ORCPT ); Fri, 14 Jul 2017 04:24:01 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:35144 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750853AbdGNIYA (ORCPT ); Fri, 14 Jul 2017 04:24:00 -0400 Received: by mail-wm0-f65.google.com with SMTP id u23so9488625wma.2 for ; Fri, 14 Jul 2017 01:23:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=rLMmBCvR/5JSmLmaTzblkHkU8Mq98xifOT7ITmekSfU=; b=dD9vg2GNwi2lMVZslKqe7e8ETzGUUriFg1CCk/931RtOGnZjYGTYRHUHhbC2+RGK72 ns0QO+UqXpjvLU9yxPTg/1UizaN0epXICqZ1YaDwwWbnGl+y9L0lf8asDMtpo5US+ocI CU7E4P+4XZteWriftq4T8WbbhSG2L5A7T3QLEKwHVu2eVz2cia06s55V4E+W5d/rlAte P/C/3fYoToe8Crcsb99LFsy3OVZ0ZUP/Iq4lU+pUYvA8cus7ENzfAo1fYNuSfc/GhcDD 418OelT7DhIByRNDz3azxJSKL3v2KYB9tTpJ+dD5/HH2LsSA/9yPR7VzH/aQt3AHmmIc 5kyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=rLMmBCvR/5JSmLmaTzblkHkU8Mq98xifOT7ITmekSfU=; b=qR32YdbsK4XsgjIO7hMW4Su3DKQ+jnu4yATSWw77Fk53jtllMs72xB7BmOHxumCyUT pQ+8sWqTN6YAZNdqFn59CKaq8v+WSwECcI+4vsVO0niTzgUviQmUqsE25Adv6EF2uds3 UGTQEoYaavozlTRTrt7IhKGXvyO1GEELUVQ3coytww2/2DM9w1lPcX+wN5ynqt81aUEu YyIu2h9Ybx2F1n7Abqk96VBCKuP/GLI0m9ZpnzxkPzbtrCwBrNp0TII+Z2CgU28NpGtR gnuYIe0QTJxkWTsfZwTUQCB+SYGPhGlNMF4iY82CnZYij81PXJ3QWP9Wl3jd90SUhNHY lNpA== X-Gm-Message-State: AIVw111YMhU5WN/BhPX8g0+K0MHV9rWHu81nnX+35TrbfVVCxEJYVe7V 5ek0T7lNQU8CiA== X-Received: by 10.28.35.201 with SMTP id j192mr1754007wmj.26.1500020638756; Fri, 14 Jul 2017 01:23:58 -0700 (PDT) Received: from mephisto.homenet.telecomitalia.it (host157-150-dynamic.54-79-r.retail.telecomitalia.it. [79.54.150.157]) by smtp.gmail.com with ESMTPSA id m123sm2213956wmb.3.2017.07.14.01.23.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Jul 2017 01:23:57 -0700 (PDT) From: Carlo Caione To: mturquette@baylibre.com, linux-clk@vger.kernel.org, dvhart@infradead.org, pierre-louis.bossart@linux.intel.com, sboyd@codeaurora.org, linux@endlessm.com, eballetbo@gmail.com, andriy.shevchenko@linux.intel.com Cc: Carlo Caione Subject: [PATCH v3] clk: x86: Do not gate clocks enabled by the firmware Date: Fri, 14 Jul 2017 10:23:56 +0200 Message-Id: <20170714082356.28117-1-carlo@caione.org> X-Mailer: git-send-email 2.13.2 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by: Enric Balletbo i Serra Acked-by: Andy Shevchenko Acked-by: Darren Hart (VMware) Signed-off-by: Carlo Caione --- drivers/clk/x86/clk-pmc-atom.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/x86/clk-pmc-atom.c b/drivers/clk/x86/clk-pmc-atom.c index 2b60577703ef..be8d821ce625 100644 --- a/drivers/clk/x86/clk-pmc-atom.c +++ b/drivers/clk/x86/clk-pmc-atom.c @@ -185,6 +185,13 @@ static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id, pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; spin_lock_init(&pclk->lock); + /* + * If the clock was already enabled by the firmware mark it as critical + * to avoid it being gated by the clock framework if no driver owns it. + */ + if (plt_clk_is_enabled(&pclk->hw)) + init.flags |= CLK_IS_CRITICAL; + ret = devm_clk_hw_register(&pdev->dev, &pclk->hw); if (ret) { pclk = ERR_PTR(ret);