From patchwork Mon Aug 7 14:51:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 9885507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 474F2603B4 for ; Mon, 7 Aug 2017 14:52:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3898228429 for ; Mon, 7 Aug 2017 14:52:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D14C2868F; Mon, 7 Aug 2017 14:52:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A717328671 for ; Mon, 7 Aug 2017 14:52:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751704AbdHGOwI (ORCPT ); Mon, 7 Aug 2017 10:52:08 -0400 Received: from mail-pg0-f41.google.com ([74.125.83.41]:34743 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751564AbdHGOwH (ORCPT ); Mon, 7 Aug 2017 10:52:07 -0400 Received: by mail-pg0-f41.google.com with SMTP id u185so2629123pgb.1 for ; Mon, 07 Aug 2017 07:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ec0e2Nq7ie2h6qzkkcAuRYquTK7yvRG0FnBEZ5KqHZM=; b=MUi+b2n1nfeAGzhAZEPiyazF+Nl2dIUEcBH/j5aJ/qGMn/7ox9zfUtPMG5dl83jaM5 DmzuubGM4BInnIPFZjkBFFZINMqJE+1o/YGJjYQvkSwlEWOEeoksaCMMU0a1e6RhDvdF 9MR9SHqxdAd6Ygg0dZ0xxIveOJZq5vrnSPVhw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ec0e2Nq7ie2h6qzkkcAuRYquTK7yvRG0FnBEZ5KqHZM=; b=q3QOM5pJSiz4ewwlQI5VM7D/IPJxi1ar5kIZf83sehpzMOfEml0+GHAtuuZQsTDE6m CuiekOQcXUFg6ybdMJLaG2QbFC/xd7yi0ePW61GJXEVRJyj86WI1Gr+Xs9m5QHikHwYS 3am3FOT1pIEvVdXLIKMT/Of+nPu1PnduVYGQ036AlAbqdGXBrPThlSZiMHOjgPKXgk30 N29qTT6aOk55SnnEcGjjboo132C6I3+9awiSiWPEsJ/FLWFX0gTChkknL1t7jU74ndZd 1tiOA/kACy76vH0nWKxgjm4ef1r5P76UAe68IaRfl2p+f5bhedCPMMZenHVuL/2UFjkT PrcA== X-Gm-Message-State: AHYfb5gomQWRLXa2U5rYtM2K+8G8Dbv3fg6lHWxkp2JxwzZZJRU80sJB ByUwUtOAxDfuomi3 X-Received: by 10.98.16.68 with SMTP id y65mr845361pfi.165.1502117526764; Mon, 07 Aug 2017 07:52:06 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.229]) by smtp.gmail.com with ESMTPSA id p80sm16871832pfa.19.2017.08.07.07.52.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Aug 2017 07:52:06 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org Cc: chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guodong Xu Subject: [PATCH] clk: hi3660: fix incorrect uart3 clock freqency Date: Mon, 7 Aug 2017 22:51:56 +0800 Message-Id: <20170807145156.7880-1-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Zhong Kaihua UART3 clock rate is doubled in previous commit. This error is not detected until recently a mezzanine board which makes real use of uart3 port (through LS connector of 96boards) was setup and tested on hi3660-hikey960 board. This patch changes clock source rate of clk_factor_uart3 to 100000000. Signed-off-by: Zhong Kaihua Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi3660.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index a18258e..f404199 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { /* crgctrl */ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { - { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, }, + { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, }, { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, }, { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, }, { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },