From patchwork Wed Sep 27 06:27:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 9973175 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 777606037F for ; Wed, 27 Sep 2017 06:28:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6B4C4223C6 for ; Wed, 27 Sep 2017 06:28:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 60221290A5; Wed, 27 Sep 2017 06:28:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E47F8223C6 for ; Wed, 27 Sep 2017 06:28:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751708AbdI0G15 (ORCPT ); Wed, 27 Sep 2017 02:27:57 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:37746 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750805AbdI0G1z (ORCPT ); Wed, 27 Sep 2017 02:27:55 -0400 Received: by mail-pf0-f193.google.com with SMTP id e69so5991291pfg.4; Tue, 26 Sep 2017 23:27:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=BPULn7yKIJDVGVtQFe5shA3XgLvVoAxeDDXnIyJxITA=; b=LRV36CLfzJe0x6UhHdRvYIGwo7v+/AlSlOWkPNz7IBJRBbwDsigNxsvOFpUd+JADYj nh66W9mgXeWsvSocOa/xejBqqDyWO9dGQ4txZJkAOpWqFyN9jaf04lzG+ySfFeNL/UO1 Ygyux2kO0NFgHu/jNQuLbX1M6ciZqhrisPzwCSX0J2sNLKmtOxn4LCkwMfZYA/gYZj7Q qHa/zjdBNWddjQMM2OiawHHBQ31WRsTwVUOTO2isvru3wgjQHmPA//pzBBCQkuywEC/g LH8v8U/jHcB78lkFigwkQMiD38RznptmIjgdXhE617DieymzUzts4NKtN+AEQ4ik++Ft +X/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=BPULn7yKIJDVGVtQFe5shA3XgLvVoAxeDDXnIyJxITA=; b=C7xhNT51XAaC6D8MZ3UQkK0eXqe0vPHfxfpedKeiqYimGL55i6wnuk+OJUKp6FhWpj W6C9wtc2GkPRYQjai6KnREZ9D4qcFhZWU6+z4c5U/xVsEWZew7sl0LkrHo8yLxy5kIhk F2vqveAsaaCqm5hTg+33L2dhsjN6Hf3hgl+/+/M+H6LbPcqtw4fsYeTOjNkcdkbfQg1V KZRvekpNdvRPzy47fAQ2CNhTyFMVxfEBPb6Wfr/JsECPpI/swCpedsHSbHupP5SHGg/1 BijKA6b6BWdSeuDAivBcww8s46GyhGCv3NIeZBCnvu9cpaC8N8dFtA2rz6jcCwfYb6A+ l0DQ== X-Gm-Message-State: AHPjjUiM96nOk4/3CJxFTkZJVWyzJ/ZCVqjzfU2SZmt8/ojtFmFunnux FvlYcDIhXBMU5cEPSxwji+Q= X-Google-Smtp-Source: AOwi7QDXa6FocIOjS0j77Pbpo0pm3bWLgLkVxUAyaI5yz7yxVtC8mhdug9HwOVz1J5rD2RWDtCsDmA== X-Received: by 10.159.198.72 with SMTP id y8mr355824plt.410.1506493674675; Tue, 26 Sep 2017 23:27:54 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id f13sm20434397pfj.127.2017.09.26.23.27.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Sep 2017 23:27:52 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Wed, 27 Sep 2017 15:57:44 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v3 3/5] clk: aspeed: Add platform driver and register PLLs Date: Wed, 27 Sep 2017 15:57:00 +0930 Message-Id: <20170927062702.11350-4-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170927062702.11350-1-joel@jms.id.au> References: <20170927062702.11350-1-joel@jms.id.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley --- v3: - Fix bclk and eclk calculation - Seperate out ast2400 and ast25000 for pll calculation Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 127 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 14387055554f..e43016ea82cd 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -108,6 +110,20 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const char * const eclk_parents[] = {"d1pll", "hpll", "mpll"}; + +static const struct clk_div_table ast2500_mac_div_table[] = { + { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + static const struct clk_div_table ast2400_div_table[] = { { 0x0, 2 }, { 0x1, 4 }, @@ -173,6 +189,117 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) mult, div); } +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *mac_div_table; + struct clk_hw *(*calc_pll)(const char *name, u32 val); +}; + +static const struct aspeed_clk_soc_data ast2500_data = { + .div_table = ast2500_div_table, + .mac_div_table = ast2500_mac_div_table, + .calc_pll = aspeed_ast2500_calc_pll, +}; + +static const struct aspeed_clk_soc_data ast2400_data = { + .div_table = ast2400_div_table, + .mac_div_table = ast2400_div_table, + .calc_pll = aspeed_ast2400_calc_pll, +}; + +static int __init aspeed_clk_probe(struct platform_device *pdev) +{ + const struct aspeed_clk_soc_data *soc_data; + struct device *dev = &pdev->dev; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + /* SoC generations share common layouts but have different divisors */ + soc_data = of_device_get_match_data(&pdev->dev); + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_MISC_CTRL, &val); + if (val & BIT(12)) + rate = 24000000 / 13; + else + rate = 24000000; + /* TODO: Find the parent data for the uart clock */ + hw = clk_hw_register_fixed_rate(NULL, "uart", NULL, 0, rate); + aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* + * Memory controller (M-PLL) PLL. This clock is configured by the + * bootloader, and is exposed to Linux as a read-only clock rate. + */ + regmap_read(map, ASPEED_MPLL_PARAM, &val); + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = soc_data->calc_pll("mpll", val); + + /* SD/SDIO clock divider (TODO: There's a gate too) */ + hw = clk_hw_register_divider_table(NULL, "sdio", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC AHB bus clock divider */ + hw = clk_hw_register_divider_table(NULL, "mac", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, + soc_data->mac_div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(NULL, "lhclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* Video Engine (ECLK) mux and clock divider */ + hw = clk_hw_register_mux(NULL, "eclk_mux", + eclk_parents, ARRAY_SIZE(eclk_parents), 0, + scu_base + ASPEED_CLK_SELECTION, 2, 2, + 0, &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; + hw = clk_hw_register_divider_table(NULL, "eclk", "eclk_mux", 0, + scu_base + ASPEED_CLK_SELECTION, 28, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw; + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(NULL, "bclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, + soc_data->div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + return 0; +}; + +static const struct of_device_id aspeed_clk_dt_ids[] = { + { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, + { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, + { }, +}; + +static struct platform_driver aspeed_clk_driver = { + .probe = aspeed_clk_probe, + .driver = { + .name = "aspeed-clk", + .of_match_table = aspeed_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_clk_driver); + static void __init aspeed_ast2400_cc(struct regmap *map) { struct clk_hw *hw;