From patchwork Thu Nov 2 06:56:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10038069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 797B4603B5 for ; Thu, 2 Nov 2017 07:09:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CAEA28E03 for ; Thu, 2 Nov 2017 07:09:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 615ED28E04; Thu, 2 Nov 2017 07:09:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4E5528E05 for ; Thu, 2 Nov 2017 07:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754791AbdKBHJN (ORCPT ); Thu, 2 Nov 2017 03:09:13 -0400 Received: from sci-ig2.spreadtrum.com ([222.66.158.135]:61534 "EHLO SHSQR01.spreadtrum.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1752738AbdKBHJM (ORCPT ); Thu, 2 Nov 2017 03:09:12 -0400 Received: from ig2.spreadtrum.com (shmbx04.spreadtrum.com [10.0.1.214]) by SHSQR01.spreadtrum.com with ESMTP id vA272XpH016235 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 2 Nov 2017 15:02:33 +0800 (CST) (envelope-from Chunyan.Zhang@spreadtrum.com) Received: from SHCAS02.spreadtrum.com (10.0.1.202) by SHMBX04.spreadtrum.com (10.0.1.214) with Microsoft SMTP Server (TLS) id 15.0.847.32; Thu, 2 Nov 2017 15:02:35 +0800 Received: from localhost (10.0.73.143) by SHCAS02.spreadtrum.com (10.0.1.250) with Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend Transport; Thu, 2 Nov 2017 15:02:35 +0800 From: Chunyan Zhang To: Stephen Boyd , Michael Turquette , Rob Herring , Mark Rutland CC: Catalin Marinas , Will Deacon , , , Arnd Bergmann , Mark Brown , Xiaolong Zhang , Ben Li , , , Orson Zhai , Chunyan Zhang Subject: [PATCH V3 07/11] clk: sprd: add composite clock support Date: Thu, 2 Nov 2017 14:56:22 +0800 Message-ID: <20171102065626.21835-8-chunyan.zhang@spreadtrum.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20171102065626.21835-1-chunyan.zhang@spreadtrum.com> References: <20171102065626.21835-1-chunyan.zhang@spreadtrum.com> MIME-Version: 1.0 X-MAIL: SHSQR01.spreadtrum.com vA272XpH016235 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch introduced composite driver for Spreadtrum's SoCs. The functions of this composite clock simply consist of divider and mux clocks. Signed-off-by: Chunyan Zhang --- drivers/clk/sprd/Makefile | 1 + drivers/clk/sprd/composite.c | 65 ++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/sprd/composite.h | 49 +++++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 drivers/clk/sprd/composite.c create mode 100644 drivers/clk/sprd/composite.h diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile index 80e6039..2262e76 100644 --- a/drivers/clk/sprd/Makefile +++ b/drivers/clk/sprd/Makefile @@ -4,3 +4,4 @@ clk-sprd-y += common.o clk-sprd-y += gate.o clk-sprd-y += mux.o clk-sprd-y += div.o +clk-sprd-y += composite.o diff --git a/drivers/clk/sprd/composite.c b/drivers/clk/sprd/composite.c new file mode 100644 index 0000000..30d5b36 --- /dev/null +++ b/drivers/clk/sprd/composite.c @@ -0,0 +1,65 @@ +/* + * Spreadtrum composite clock driver + * + * Copyright (C) 2017 Spreadtrum, Inc. + * Author: Chunyan Zhang + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include + +#include "composite.h" + +DEFINE_SPINLOCK(sprd_comp_lock); +EXPORT_SYMBOL_GPL(sprd_comp_lock); + +static long sprd_comp_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct sprd_comp *cc = hw_to_sprd_comp(hw); + + return sprd_div_helper_round_rate(&cc->common, &cc->div, + rate, parent_rate); +} + +static unsigned long sprd_comp_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct sprd_comp *cc = hw_to_sprd_comp(hw); + + return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate); +} + +static int sprd_comp_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct sprd_comp *cc = hw_to_sprd_comp(hw); + + return sprd_div_helper_set_rate(&cc->common, &cc->div, + rate, parent_rate); +} + +static u8 sprd_comp_get_parent(struct clk_hw *hw) +{ + struct sprd_comp *cc = hw_to_sprd_comp(hw); + + return sprd_mux_helper_get_parent(&cc->common, &cc->mux); +} + +static int sprd_comp_set_parent(struct clk_hw *hw, u8 index) +{ + struct sprd_comp *cc = hw_to_sprd_comp(hw); + + return sprd_mux_helper_set_parent(&cc->common, &cc->mux, index); +} + +const struct clk_ops sprd_comp_ops = { + .get_parent = sprd_comp_get_parent, + .set_parent = sprd_comp_set_parent, + + .round_rate = sprd_comp_round_rate, + .recalc_rate = sprd_comp_recalc_rate, + .set_rate = sprd_comp_set_rate, +}; +EXPORT_SYMBOL_GPL(sprd_comp_ops); diff --git a/drivers/clk/sprd/composite.h b/drivers/clk/sprd/composite.h new file mode 100644 index 0000000..551f274 --- /dev/null +++ b/drivers/clk/sprd/composite.h @@ -0,0 +1,49 @@ +/* + * Spreadtrum composite clock driver + * + * Copyright (C) 2017 Spreadtrum, Inc. + * Author: Chunyan Zhang + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SPRD_COMPOSITE_H_ +#define _SPRD_COMPOSITE_H_ + +#include "common.h" +#include "mux.h" +#include "div.h" + +struct sprd_comp { + struct sprd_mux_internal mux; + struct sprd_div_internal div; + struct sprd_clk_common common; +}; + +#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _table, \ + _mshift, _mwidth, _dshift, _dwidth, _flags) \ + struct sprd_comp _struct = { \ + .mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \ + .div = _SPRD_DIV_CLK(_dshift, _dwidth), \ + .common = { \ + .regmap = NULL, \ + .reg = _reg, \ + .lock = &sprd_comp_lock, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parent, \ + &sprd_comp_ops, \ + _flags), \ + } \ + } + +static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw) +{ + struct sprd_clk_common *common = hw_to_sprd_clk_common(hw); + + return container_of(common, struct sprd_comp, common); +} + +extern const struct clk_ops sprd_comp_ops; +extern spinlock_t sprd_comp_lock; + +#endif /* _SPRD_COMPOSITE_H_ */