From patchwork Tue Nov 14 12:20:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 10057463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D3FBF6023A for ; Tue, 14 Nov 2017 12:20:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A790829268 for ; Tue, 14 Nov 2017 12:20:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9AE0C29748; Tue, 14 Nov 2017 12:20:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA5A629268 for ; Tue, 14 Nov 2017 12:20:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754969AbdKNMU0 (ORCPT ); Tue, 14 Nov 2017 07:20:26 -0500 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111]:43972 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754950AbdKNMUZ (ORCPT ); Tue, 14 Nov 2017 07:20:25 -0500 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 0ADAB10C1362; Tue, 14 Nov 2017 04:20:25 -0800 (PST) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id DC00C22F; Tue, 14 Nov 2017 04:20:24 -0800 (PST) Received: from localhost.internal.synopsys.com (unknown [10.121.8.106]) by mailhost.synopsys.com (Postfix) with ESMTP id B83E7220; Tue, 14 Nov 2017 04:20:22 -0800 (PST) From: Eugeniy Paltsev To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Eugeniy Paltsev Subject: [PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree Date: Tue, 14 Nov 2017 15:20:20 +0300 Message-Id: <20171114122020.9800-1-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add option to set initial output frequency of plls via "clock-frequency" property in pll's device tree node. This frequency will be set while pll driver probed. The usage example is setting CPU clock frequency on boot See discussion: https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html Signed-off-by: Eugeniy Paltsev --- .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- 4 files changed, 74 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt index c56c755..5703059 100644 --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt @@ -13,6 +13,10 @@ Required properties: - clocks: shall be the input parent clock phandle for the PLL. - #clock-cells: from common clock binding; Should always be set to 0. +Optional properties: +- clock-frequency: output frequency generated by pll in Hz which will be set +while probing. Should be a single cell. + Example: input_clk: input-clk { clock-frequency = <33333333>; @@ -25,4 +29,5 @@ Example: reg = <0x00 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + clock-frequency = <1000000000>; }; diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt index 11fe487..5908f99 100644 --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. - clocks: shall be the input parent clock phandle for the PLL. - #clock-cells: from common clock binding; Should always be set to 0. +Optional properties: +- clock-frequency: output frequency generated by pll in Hz which will be set +while probing. Should be a single cell. + Example: input-clk: input-clk { clock-frequency = <33333333>; @@ -25,4 +29,5 @@ Example: reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input-clk>; + clock-frequency = <100000000>; }; diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c index 25d8c24..3f4345d 100644 --- a/drivers/clk/axs10x/pll_clock.c +++ b/drivers/clk/axs10x/pll_clock.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = { .set_rate = axs10x_pll_set_rate, }; +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +{ + u32 requested_rate; + + /* If we specify initial pll output frequency try to set it */ + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) + return; + + if (clk_prepare_enable(clk)) { + pr_err("Cannot enable %s clock.\n", node->name); + return; + } + + if (clk_set_rate(clk, requested_rate)) + pr_err("Cannot set %s clock rate.\n", node->name); + + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +} + static int axs10x_pll_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, - &pll_clk->hw); + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll_clk->hw); + if (ret) + return ret; + + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); + + return 0; } static int axs10x_pll_clk_remove(struct platform_device *pdev) @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node) goto err_unregister_clk; } + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, node); + return; err_unregister_clk: diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c index bbf23717..74fd006 100644 --- a/drivers/clk/clk-hsdk-pll.c +++ b/drivers/clk/clk-hsdk-pll.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = { .set_rate = hsdk_pll_set_rate, }; +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +{ + u32 requested_rate; + + /* If we specify initial pll output frequency try to set it */ + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) + return; + + if (clk_prepare_enable(clk)) { + pr_err("Cannot enable %s clock.\n", node->name); + return; + } + + if (clk_set_rate(clk, requested_rate)) + pr_err("Cannot set %s clock rate.\n", node->name); + + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +} + static int hsdk_pll_clk_probe(struct platform_device *pdev) { int ret; @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, - &pll_clk->hw); + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll_clk->hw); + if (ret) + return ret; + + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); + + return 0; } static int hsdk_pll_clk_remove(struct platform_device *pdev) @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node) goto err_unmap_spec_regs; } + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, node); + return; err_unmap_spec_regs: