From patchwork Fri Dec 22 02:45:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 10128709 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B97856038F for ; Fri, 22 Dec 2017 02:46:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A9B6E2993E for ; Fri, 22 Dec 2017 02:46:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9E5F82997D; Fri, 22 Dec 2017 02:46:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 11E3D2993E for ; Fri, 22 Dec 2017 02:46:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756131AbdLVCqa (ORCPT ); Thu, 21 Dec 2017 21:46:30 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34665 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755893AbdLVCq0 (ORCPT ); Thu, 21 Dec 2017 21:46:26 -0500 Received: by mail-pf0-f195.google.com with SMTP id a90so14782978pfk.1; Thu, 21 Dec 2017 18:46:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=tpR8qyGU2q4CSR7ehBU5bjr+Vz3UbL3xFgSfK2SiWZA=; b=pVl98C49gEzktXvp3CZ8AddwhHGhSIkDwn6pC4GQM/iv32omL3Ox/nnDhh82t3BsAF HNUBXwaAwpFDsIPUtspsnzJhRMFEeOl3C9NLpfYn9oA/Z2yQ0NhTz2LO5T7PBJjcoYPR LuqvZXbAU+xn8rhpGF137mW4f0Bsj3v18avrxMuapfGmSzyeEajiD7Cyo4f1u5b1kFsf SrFtUvcpbIg3kiHmNiRaJrNQ1a8IYZZVAEdUTDpFxp7fMJy6mIer56hYu6yVu5DdQNb0 lYK5kFPt/5gKeVYeDkWyrzrZ+7K90pFKDY32cimabAJTY4s2m6vLlfNP4/P2qOn7jpKL Dgog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=tpR8qyGU2q4CSR7ehBU5bjr+Vz3UbL3xFgSfK2SiWZA=; b=QfcqH0H2vrvE89QqGtOeTj0y3jfm6FeX9vE3wo+nijTbLMuvFgNbOc95TFhISAobLv H7YsGKhA2MOY3eqI6HqgwnlC0+zbzQCCW/CXCEV76JB8VNwGfYJLO10sGI8HSmN2DMKD Ywx9IqVxv1dfY+KjLqz4MX4uVk1SxKX8GcA2L86V2bUIYc68VLG58DAzu5Tb8Q1IpBjD LZidNNo3M1rgEEowDUaOvHLBTeotaJR8KpUGdwXVuMVKLzUigzQyJnWXrA3AzfA8kUHg tWmd29bGxd01n6tyMzgXoMElOfVIZC+3WvLWA5d088IVeyoVoPNDNayOrkaB/PMDCH9Q SJKQ== X-Gm-Message-State: AKGB3mJnSw9u7fg+xt3A1OvKsTN2SYf9h3mwWikjnEr+9KuJcRv6+0/n 5eugsKptCb++mSCL403fyoM= X-Google-Smtp-Source: ACJfBosskSKyXxyGFMNOKQFrGusZHGCz8zv0gX8qPWWd1jHT7aAsFJX/JcEN9dJb+8LAshWQL0vehg== X-Received: by 10.99.96.10 with SMTP id u10mr11382115pgb.303.1513910786277; Thu, 21 Dec 2017 18:46:26 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id u6sm42720595pfk.126.2017.12.21.18.46.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Dec 2017 18:46:25 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 22 Dec 2017 13:16:16 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v7 5/5] clk: aspeed: Add reset controller Date: Fri, 22 Dec 2017 13:15:22 +1030 Message-Id: <20171222024522.10362-6-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171222024522.10362-1-joel@jms.id.au> References: <20171222024522.10362-1-joel@jms.id.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are some resets that are not associated with gates. These are represented by a reset controller. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley Reviewed-by: Benjamin Herrenschmidt --- v7: - Rebase on dt-bindings patch v5: - Add Andrew's Reviewed-by v3: - Add named initalisers for the reset defines - Add define for ADC --- drivers/clk/clk-aspeed.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index dbd3c7774831..6fb344730cea 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -267,6 +268,68 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +static const u8 aspeed_resets[] = { + [ASPEED_RESET_XDMA] = 25, + [ASPEED_RESET_MCTP] = 24, + [ASPEED_RESET_ADC] = 23, + [ASPEED_RESET_JTAG_MASTER] = 22, + [ASPEED_RESET_MIC] = 18, + [ASPEED_RESET_PWM] = 9, + [ASPEED_RESET_PCIVGA] = 8, + [ASPEED_RESET_I2C] = 2, + [ASPEED_RESET_AHB] = 1, +}; + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 val, rst = BIT(aspeed_resets[id]); + int ret; + + ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_reset_ops = { + .assert = aspeed_reset_assert, + .deassert = aspeed_reset_deassert, + .status = aspeed_reset_status, +}; + static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, @@ -308,10 +371,11 @@ static int aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; struct device *dev = &pdev->dev; + struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; - int i; + int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -319,6 +383,22 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(map); } + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); + ar->rcdev.ops = &aspeed_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(dev); if (!soc_data) {