From patchwork Tue May 15 11:22:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 10400821 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3845D601F9 for ; Tue, 15 May 2018 11:23:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E5D32874C for ; Tue, 15 May 2018 11:23:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 12C8B28756; Tue, 15 May 2018 11:23:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D68028755 for ; Tue, 15 May 2018 11:23:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752671AbeEOLXb (ORCPT ); Tue, 15 May 2018 07:23:31 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:23258 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752740AbeEOLXa (ORCPT ); Tue, 15 May 2018 07:23:30 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w4FBMTaD015707; Tue, 15 May 2018 06:22:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1526383349; bh=nObnmzey7WXcpiadPHTqd9FAm9spUClcQVo5F+0vXTs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pgYWIHvxd4bpTlrSYf089f3dRhv8gwnK8SdHWzauUhaTYF5gaeVGTcVy1YccdORar 29oqIWIBajF/KuDIJbZyYLJxnmKUJ6z/04uMac+vehmrKJI3c9vOYTB5wn7AYoLaUu MQiRX+MFu4A1Lt4suFhnNQnakbUiGKQXaKImQCtY= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4FBMTJ7029808; Tue, 15 May 2018 06:22:29 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 15 May 2018 06:22:29 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 15 May 2018 06:22:29 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4FBMO7E007225; Tue, 15 May 2018 06:22:27 -0500 From: Sekhar Nori To: David Lechner , Michael Turquette , Stephen Boyd CC: Linux clk Mailing List , Linux ARM Mailing List , Sekhar Nori , Kevin Hilman Subject: [PATCH v2 1/2] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled Date: Tue, 15 May 2018 16:52:23 +0530 Message-ID: <20180515112224.30122-2-nsekhar@ti.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180515112224.30122-1-nsekhar@ti.com> References: <20180515112224.30122-1-nsekhar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot be disabled. Mark it so to prevent unused clock disable infrastructure from disabling it. Signed-off-by: Sekhar Nori Reviewed-by: David Lechner --- v2: rebased to apply to v4.17-rc1. No functional change. drivers/clk/davinci/pll-dm646x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/davinci/pll-dm646x.c b/drivers/clk/davinci/pll-dm646x.c index a61cc3256418..0ae827e3ce80 100644 --- a/drivers/clk/davinci/pll-dm646x.c +++ b/drivers/clk/davinci/pll-dm646x.c @@ -72,7 +72,7 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = { .flags = 0, }; -SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0); +SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED); int dm646x_pll2_init(struct device *dev, void __iomem *base) {