From patchwork Thu May 24 05:23:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 10422681 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B517E6019D for ; Thu, 24 May 2018 05:24:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A270E28AB2 for ; Thu, 24 May 2018 05:24:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9518D29311; Thu, 24 May 2018 05:24:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 426DC28AB2 for ; Thu, 24 May 2018 05:23:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751563AbeEXFX6 (ORCPT ); Thu, 24 May 2018 01:23:58 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:58114 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751158AbeEXFX6 (ORCPT ); Thu, 24 May 2018 01:23:58 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id A02C583645; Thu, 24 May 2018 17:23:55 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1527139435; bh=vLRkad/g14QwhX8qsxS2Ny2HZInKOW2xX9IXwRWUxgo=; h=From:To:Cc:Subject:Date; b=rNUetJ7vzKyC47QwSD48AGaRiLrZeSYBnp+Wa6RphrOGCcm1V8nIFzWhwRX8mHLWB JEnSElnI/TeLezWEqUJgWXQkCNiy9CSMPsx1ybsG5Encu1ZahSbYpJ2wqU/H7UMvD0 htI/iUun+hIibe4eB63SFlv2jX7c7134GaeG3eAs= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 24 May 2018 17:23:56 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 3AA3013EEFA; Thu, 24 May 2018 17:23:57 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 660091E091C; Thu, 24 May 2018 17:23:55 +1200 (NZST) From: Chris Packham To: sboyd@kernel.org, linux-clk@vger.kernel.org Cc: Chris Packham , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND Date: Thu, 24 May 2018 17:23:41 +1200 Message-Id: <20180524052341.12422-1-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.17.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The correct fieldbit value for the NAND PLL reload trigger is 27. Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") Signed-off-by: Chris Packham --- I can't remember where the value of 26 came from. Looking at the lsp source I have from Marvell it's always been 27, so I suspect I just messed up when porting. The only documentation I have is that register field is bits 21:27 without adding any detail as to which clock trees correspond to the individual bits so I'm not sure which clock tree was being triggered. drivers/clk/mvebu/clk-corediv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index 8491979f4096..68f05c53d40e 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = { }; static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = { - { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */ + { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */ }; #define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)