From patchwork Sun May 27 21:54:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 10429581 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 713BD602CC for ; Sun, 27 May 2018 21:55:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6EF3228B74 for ; Sun, 27 May 2018 21:55:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 62C3928B9A; Sun, 27 May 2018 21:55:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF59E28B74 for ; Sun, 27 May 2018 21:55:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752230AbeE0Vy4 (ORCPT ); Sun, 27 May 2018 17:54:56 -0400 Received: from mail.kmu-office.ch ([178.209.48.109]:45052 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752009AbeE0Vyv (ORCPT ); Sun, 27 May 2018 17:54:51 -0400 Received: from trochilidae.lan (unknown [37.17.239.3]) by mail.kmu-office.ch (Postfix) with ESMTPSA id 085935C19CF; Sun, 27 May 2018 23:54:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1527458089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:content-type:content-transfer-encoding: in-reply-to:references; bh=//eIlLZe1T46YZzfMl0IFhnnH7r3RKHdNRqL0Zm0JLQ=; b=JiL5QvnPmuUHhmIX/dHLTA9h7YNzlcFRTMgpYpNs6Ej70rzZw7D3EqcEovEzckeGzHs/HV Ge24W1t20iMNnxjV3HPsScPWoXCtCwaHNeRu00m/yg6qMuVrhPYJCPa/N7VZ3H7F/SyzV0 Ilg2vggwm59tFsYs4HcUnX17MTRiTyg= From: Stefan Agner To: boris.brezillon@bootlin.com, dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: dev@lynxeye.de, miquel.raynal@bootlin.com, richard@nod.at, marcel@ziswiler.com, krzk@kernel.org, digetx@gmail.com, benjamin.lindqvist@endian.se, jonathanh@nvidia.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mirza.krak@gmail.com, linux-mtd@lists.infradead.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Stefan Agner Subject: [PATCH v2 2/6] mtd: rawnand: tegra: add devicetree binding Date: Sun, 27 May 2018 23:54:38 +0200 Message-Id: <20180527215442.14760-3-stefan@agner.ch> X-Mailer: git-send-email 2.17.0 X-Spamd-Result: default: False [-2.10 / 15.00]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[26]; BAYES_HAM(-3.00)[100.00%]; TAGGED_RCPT(0.00)[dt]; MIME_GOOD(-0.10)[text/plain]; FROM_HAS_DN(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_ZERO(0.00)[0]; MID_CONTAINS_FROM(1.00)[]; ASN(0.00)[asn:13030, ipnet:37.17.238.0/23, country:CH]; RCVD_TLS_ALL(0.00)[]; ARC_NA(0.00)[] Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lucas Stach This adds the devicetree binding for the Tegra 2 NAND flash controller. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner --- .../bindings/mtd/nvidia,tegra20-nand.txt | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt new file mode 100644 index 000000000000..49e472af1b39 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt @@ -0,0 +1,62 @@ +NVIDIA Tegra NAND Flash controller + +Required properties: +- compatible: Must be one of: + - "nvidia,tegra20-nand" +- reg: MMIO address range +- interrupts: interrupt output of the NFC controller +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - nand +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - nand + +Optional children nodes: +Individual NAND chips are children of the NAND controller node. Currently +only one NAND chip supported. + +Required children node properties: +- reg: An integer ranging from 1 to 6 representing the CS line to use. + +Optional children node properties: +- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default +- nand-ecc-algo: string, algorithm of NAND ECC. + Supported values are: "rs", "bch". +- nand-bus-width : 8 or 16 bus width if not present 8 +- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false +- nand-ecc-strength: integer representing the number of bits to correct + per ECC step. Supported strength using HW ECC modes are: + - RS: 4, 6, 8 + - BCH: 4, 8, 14, 16 +- nand-ecc-step-size: integer representing the number of data bytes + that are covered by a single ECC step. Must be 512. +- wp-gpios: GPIO specifier for the write protect pin. + +Optional child node of NAND chip nodes: +Partitions: see partition.txt + + Example: + nand@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + + nand-chip@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-on-flash-bbt; + nand-ecc-algo = "bch"; + nand-ecc-step-size = <512>; + nand-ecc-strength = <8>; + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + };