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[176.162.151.233]) by smtp.gmail.com with ESMTPSA id l10-v6sm9419660wrm.29.2018.05.28.10.34.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 May 2018 10:34:22 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= To: Colin Didier , Sascha Hauer , Fabio Estevam Cc: Shawn Guo , NXP Linux Team , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Cl=C3=A9ment=20Peron?= Subject: [PATCH 3/5] Documentation: DT: add i.MX EPIT timer binding Date: Mon, 28 May 2018 19:34:10 +0200 Message-Id: <20180528173412.10000-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180528173412.10000-1-peron.clem@gmail.com> References: <20180528173412.10000-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Clément Peron Add devicetree binding document for NXP's i.MX SoC specific EPIT timer driver. Signed-off-by: Clément Peron --- .../devicetree/bindings/clock/imx6q,epit.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx6q,epit.txt diff --git a/Documentation/devicetree/bindings/clock/imx6q,epit.txt b/Documentation/devicetree/bindings/clock/imx6q,epit.txt new file mode 100644 index 000000000000..d54d455cebdc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6q,epit.txt @@ -0,0 +1,25 @@ +Binding for the i.MX6 EPIT timer + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: should be "fsl,imx6q-epit" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: Should contain EPIT controller interrupt +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names : as described in the clock bindings + +Example: + epit1: epit@20d0000 { + compatible = "fsl,imx6q-epit"; + reg = <0x020d0000 0x4000>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_EPIT1>, + <&clks IMX6QDL_CLK_IPG_PER>, + <&clks IMX6QDL_CLK_CKIL>; + clock-names = "ipg", "per", "ckil"; + };