From patchwork Fri Jun 1 06:58:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksij Rempel X-Patchwork-Id: 10442531 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3C7AA601D3 for ; Fri, 1 Jun 2018 06:58:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C15828F86 for ; Fri, 1 Jun 2018 06:58:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2061529013; Fri, 1 Jun 2018 06:58:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D72028F86 for ; Fri, 1 Jun 2018 06:58:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751131AbeFAG6g (ORCPT ); Fri, 1 Jun 2018 02:58:36 -0400 Received: from metis.ext.pengutronix.de ([85.220.165.71]:34121 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751129AbeFAG6d (ORCPT ); Fri, 1 Jun 2018 02:58:33 -0400 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1fOe12-0003qQ-9w; Fri, 01 Jun 2018 08:58:24 +0200 Received: from ore by dude.hi.pengutronix.de with local (Exim 4.91) (envelope-from ) id 1fOe11-0007OP-DI; Fri, 01 Jun 2018 08:58:23 +0200 From: Oleksij Rempel To: Shawn Guo , Fabio Estevam , Rob Herring , Mark Rutland Cc: Oleksij Rempel , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 4/4] mailbox: Add support for i.MX7D messaging unit Date: Fri, 1 Jun 2018 08:58:21 +0200 Message-Id: <20180601065821.28234-5-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180601065821.28234-1-o.rempel@pengutronix.de> References: <20180601065821.28234-1-o.rempel@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Mailbox controller is able to send messages (up to 4 32 bit words) between the endpoints. This driver was tested using the mailbox-test driver sending messages between the Cortex-A7 and the Cortex-M4. Signed-off-by: Oleksij Rempel --- drivers/mailbox/Kconfig | 6 + drivers/mailbox/Makefile | 2 + drivers/mailbox/imx-mailbox.c | 289 ++++++++++++++++++++++++++++++++++ 3 files changed, 297 insertions(+) create mode 100644 drivers/mailbox/imx-mailbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index a2bb27446dce..e1d2738a2e4c 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -15,6 +15,12 @@ config ARM_MHU The controller has 3 mailbox channels, the last of which can be used in Secure mode only. +config IMX_MBOX + tristate "iMX Mailbox" + depends on SOC_IMX7D || COMPILE_TEST + help + Mailbox implementation for iMX7D Messaging Unit (MU). + config PLATFORM_MHU tristate "Platform MHU Mailbox" depends on OF diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index cc23c3a43fcd..ba2fe1b6dd62 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o obj-$(CONFIG_ARM_MHU) += arm_mhu.o +obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o + obj-$(CONFIG_PLATFORM_MHU) += platform_mhu.o obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c new file mode 100644 index 000000000000..2bc9f11393b1 --- /dev/null +++ b/drivers/mailbox/imx-mailbox.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Pengutronix, Oleksij Rempel + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Transmit Register */ +#define IMX_MU_xTRn(x) (0x00 + 4 * (x)) +/* Receive Register */ +#define IMX_MU_xRRn(x) (0x10 + 4 * (x)) +/* Status Register */ +#define IMX_MU_xSR 0x20 +#define IMX_MU_xSR_TEn(x) BIT(20 + (x)) +#define IMX_MU_xSR_RFn(x) BIT(24 + (x)) +#define IMX_MU_xSR_BRDIP BIT(9) + +/* Control Register */ +#define IMX_MU_xCR 0x24 +/* Transmit Interrupt Enable */ +#define IMX_MU_xCR_TIEn(x) BIT(20 + (x)) +/* Receive Interrupt Enable */ +#define IMX_MU_xCR_RIEn(x) BIT(24 + (x)) + +#define IMX_MU_MAX_CHANS 4u + +struct imx_mu_priv; + +struct imx_mu_cfg { + unsigned int chans; + void (*init_hw)(struct imx_mu_priv *priv); +}; + +struct imx_mu_con_priv { + int irq; + unsigned int bidx; + unsigned int idx; +}; + +struct imx_mu_priv { + struct device *dev; + const struct imx_mu_cfg *dcfg; + void __iomem *base; + + struct mbox_controller mbox; + struct mbox_chan mbox_chans[IMX_MU_MAX_CHANS]; + + struct imx_mu_con_priv con_priv[IMX_MU_MAX_CHANS]; + struct clk *clk; +}; + +static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) +{ + return container_of(mbox, struct imx_mu_priv, mbox); +} + +static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) +{ + iowrite32(val, priv->base + offs); +} + +static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) +{ + return ioread32(priv->base + offs); +} + +static u32 imx_mu_rmw(struct imx_mu_priv *priv, u32 offs, u32 set, u32 clr) +{ + u32 val; + + val = imx_mu_read(priv, offs); + val &= ~clr; + val |= set; + imx_mu_write(priv, val, offs); + + return val; +} + +static irqreturn_t imx_mu_isr(int irq, void *p) +{ + struct mbox_chan *chan = p; + struct imx_mu_con_priv *cp = chan->con_priv; + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + + u32 val, dat; + + val = imx_mu_read(priv, IMX_MU_xSR); + val &= IMX_MU_xSR_TEn(cp->bidx) | IMX_MU_xSR_RFn(cp->bidx); + if (!val) + return IRQ_NONE; + + if (val & IMX_MU_xSR_TEn(cp->bidx)) { + imx_mu_rmw(priv, IMX_MU_xCR, 0, IMX_MU_xCR_TIEn(cp->bidx)); + mbox_chan_txdone(chan, 0); + } + + if (val & IMX_MU_xSR_RFn(cp->bidx)) { + dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx)); + mbox_chan_received_data(chan, (void *)&dat); + } + + return IRQ_HANDLED; +} + +static bool imx_mu_last_tx_done(struct mbox_chan *chan) +{ + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + struct imx_mu_con_priv *cp = chan->con_priv; + u32 val; + + val = imx_mu_read(priv, IMX_MU_xSR); + /* test if transmit register is empty */ + return (!(val & IMX_MU_xSR_TEn(cp->bidx))); +} + +static int imx_mu_send_data(struct mbox_chan *chan, void *data) +{ + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + struct imx_mu_con_priv *cp = chan->con_priv; + u32 *arg = data; + + if (imx_mu_last_tx_done(chan)) + return -EBUSY; + + imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx)); + imx_mu_rmw(priv, IMX_MU_xCR, IMX_MU_xSR_TEn(cp->bidx), 0); + + return 0; +} + +static int imx_mu_startup(struct mbox_chan *chan) +{ + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + struct imx_mu_con_priv *cp = chan->con_priv; + int ret; + + ret = request_irq(cp->irq, imx_mu_isr, + IRQF_SHARED, "imx_mu_chan", chan); + if (ret) { + dev_err(chan->mbox->dev, + "Unable to acquire IRQ %d\n", cp->irq); + return ret; + } + + imx_mu_rmw(priv, IMX_MU_xCR, IMX_MU_xCR_RIEn(cp->bidx), 0); + + return 0; +} + +static void imx_mu_shutdown(struct mbox_chan *chan) +{ + struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); + struct imx_mu_con_priv *cp = chan->con_priv; + + imx_mu_rmw(priv, IMX_MU_xCR, 0, + IMX_MU_xCR_TIEn(cp->bidx) | IMX_MU_xCR_RIEn(cp->bidx)); + + free_irq(cp->irq, chan); +} + +static const struct mbox_chan_ops imx_mu_ops = { + .send_data = imx_mu_send_data, + .startup = imx_mu_startup, + .shutdown = imx_mu_shutdown, + .last_tx_done = imx_mu_last_tx_done, +}; + +static int imx_mu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *iomem; + struct imx_mu_priv *priv; + const struct imx_mu_cfg *dcfg; + unsigned int i, chans; + int irq, ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dcfg = of_device_get_match_data(dev); + if (!dcfg) + return -EINVAL; + + priv->dcfg = dcfg; + priv->dev = dev; + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(&pdev->dev, iomem); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) + return irq < 0 ? irq : -EINVAL; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + if (PTR_ERR(priv->clk) == -ENOENT) { + priv->clk = NULL; + } else { + dev_err(dev, "Failed to get clock\n"); + return PTR_ERR(priv->clk); + } + } + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + + chans = min(dcfg->chans, IMX_MU_MAX_CHANS); + /* Initialize channel identifiers */ + for (i = 0; i < chans; i++) { + struct imx_mu_con_priv *cp = &priv->con_priv[i]; + + cp->bidx = 3 - i; + cp->idx = i; + cp->irq = irq; + priv->mbox_chans[i].con_priv = cp; + } + + priv->mbox.dev = dev; + priv->mbox.ops = &imx_mu_ops; + priv->mbox.chans = priv->mbox_chans; + priv->mbox.num_chans = chans; + priv->mbox.txdone_irq = true; + + platform_set_drvdata(pdev, priv); + + if (priv->dcfg->init_hw) + priv->dcfg->init_hw(priv); + + return mbox_controller_register(&priv->mbox); +} + +static int imx_mu_remove(struct platform_device *pdev) +{ + struct imx_mu_priv *priv = platform_get_drvdata(pdev); + + mbox_controller_unregister(&priv->mbox); + clk_disable_unprepare(priv->clk); + + return 0; +} + + +static void imx_mu_init_imx7d_a(struct imx_mu_priv *priv) +{ + /* Set default config */ + imx_mu_write(priv, 0, IMX_MU_xCR); +} + +static const struct imx_mu_cfg imx_mu_cfg_imx7d_a = { + .chans = IMX_MU_MAX_CHANS, + .init_hw = imx_mu_init_imx7d_a, +}; + +static const struct imx_mu_cfg imx_mu_cfg_imx7d_b = { + .chans = IMX_MU_MAX_CHANS, +}; + +static const struct of_device_id imx_mu_dt_ids[] = { + { .compatible = "fsl,imx7s-mu-a", .data = &imx_mu_cfg_imx7d_a }, + { .compatible = "fsl,imx7s-mu-b", .data = &imx_mu_cfg_imx7d_b }, + { }, +}; +MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); + +static struct platform_driver imx_mu_driver = { + .probe = imx_mu_probe, + .remove = imx_mu_remove, + .driver = { + .name = "imx_mu", + .of_match_table = imx_mu_dt_ids, + }, +}; +module_platform_driver(imx_mu_driver); + +MODULE_AUTHOR("Oleksij Rempel "); +MODULE_DESCRIPTION("Message Unit driver for i.MX7"); +MODULE_LICENSE("GPL v2");