| Message ID | 20180628121609.jf4dp4azeowte7pb@verge.net.au (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
Hi Simon, On Thu, Jun 28, 2018 at 2:16 PM Simon Horman <horms@verge.net.au> wrote: > On Thu, Jun 28, 2018 at 02:00:32PM +0200, Simon Horman wrote: > > On Thu, Jun 14, 2018 at 11:56:32AM +0100, Michel Pollet wrote: > > > This adds the Renesas R9A06G032 bare bone support. > > > > > > This currently only handles the SYSCTRL block note, > > > generic parts (gic, architected timer) and a UART. > > > > > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > Reviewed-by: Simon Horman <horms+renesas@verge.net.au> > > > > Thanks, applied with the following appended: > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 9d5eeff51b5f..4c85ac04872d 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1969,6 +1969,7 @@ S: Supported > > F: arch/arm/boot/dts/emev2* > > F: arch/arm/boot/dts/r7s* > > F: arch/arm/boot/dts/r8a* > > +F: arch/arm/boot/dts/r9a* > > F: arch/arm/boot/dts/sh* > > F: arch/arm/configs/shmobile_defconfig > > F: arch/arm/include/debug/renesas-scif.S > > One more update. > > dt-bindings/clock/r9a06g032-sysctrl.h is not present in v4.18-rc1, > current base of the renesas tree and likely base for the rest of the v4.19 > development cycle. > > Accordingly I have removed the include of that header and replaced > the use of symbols it defines with numeric constants. The result is below. Oh right. Thanks! > Please: > 1) Check that this is correct and Looks good to me, except for the bogus "fixes" and "SoB" below (bad squash?) > From: Michel Pollet <michel.pollet@bp.renesas.com> > Subject: [PATCH] ARM: dts: Renesas R9A06G032 base device tree file > > This adds the Renesas R9A06G032 bare bone support. > > This currently only handles the SYSCTRL block note, > generic parts (gic, architected timer) and a UART. > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > [simon: updated MAINTAINERS file > [simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet] > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > fixes ^^^^^ > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> ^^^^ Gr{oetje,eeting}s, Geert
On Thu, Jun 28, 2018 at 02:45:41PM +0200, Geert Uytterhoeven wrote: > Hi Simon, > > On Thu, Jun 28, 2018 at 2:16 PM Simon Horman <horms@verge.net.au> wrote: > > On Thu, Jun 28, 2018 at 02:00:32PM +0200, Simon Horman wrote: > > > On Thu, Jun 14, 2018 at 11:56:32AM +0100, Michel Pollet wrote: > > > > This adds the Renesas R9A06G032 bare bone support. > > > > > > > > This currently only handles the SYSCTRL block note, > > > > generic parts (gic, architected timer) and a UART. > > > > > > > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > Reviewed-by: Simon Horman <horms+renesas@verge.net.au> > > > > > > Thanks, applied with the following appended: > > > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > index 9d5eeff51b5f..4c85ac04872d 100644 > > > --- a/MAINTAINERS > > > +++ b/MAINTAINERS > > > @@ -1969,6 +1969,7 @@ S: Supported > > > F: arch/arm/boot/dts/emev2* > > > F: arch/arm/boot/dts/r7s* > > > F: arch/arm/boot/dts/r8a* > > > +F: arch/arm/boot/dts/r9a* > > > F: arch/arm/boot/dts/sh* > > > F: arch/arm/configs/shmobile_defconfig > > > F: arch/arm/include/debug/renesas-scif.S > > > > One more update. > > > > dt-bindings/clock/r9a06g032-sysctrl.h is not present in v4.18-rc1, > > current base of the renesas tree and likely base for the rest of the v4.19 > > development cycle. > > > > Accordingly I have removed the include of that header and replaced > > the use of symbols it defines with numeric constants. The result is below. > > Oh right. Thanks! > > > Please: > > 1) Check that this is correct and > > Looks good to me, except for the bogus "fixes" and "SoB" below > (bad squash?) > > > From: Michel Pollet <michel.pollet@bp.renesas.com> > > Subject: [PATCH] ARM: dts: Renesas R9A06G032 base device tree file > > > > This adds the Renesas R9A06G032 bare bone support. > > > > This currently only handles the SYSCTRL block note, > > generic parts (gic, architected timer) and a UART. > > > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > [simon: updated MAINTAINERS file > > [simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet] > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > > > fixes > ^^^^^ > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > ^^^^ > > Gr{oetje,eeting}s, Thanks, I'll remove that trailing garbage. -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/MAINTAINERS b/MAINTAINERS index 9d5eeff51b5f..4c85ac04872d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1969,6 +1969,7 @@ S: Supported F: arch/arm/boot/dts/emev2* F: arch/arm/boot/dts/r7s* F: arch/arm/boot/dts/r8a* +F: arch/arm/boot/dts/r9a* F: arch/arm/boot/dts/sh* F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi new file mode 100644 index 000000000000..339d0958011e --- /dev/null +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "renesas,r9a06g032"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clocks = <&sysctrl 84>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clocks = <&sysctrl 84>; + }; + }; + + ext_jtag_clk: extjtagclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_mclk: extmclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + + ext_rgmii_ref: extrgmiiref { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_rtc_clk: extrtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + status = "okay"; + #clock-cells = <1>; + + clocks = <&ext_mclk>, <&ext_rtc_clk>, + <&ext_jtag_clk>, <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + }; + + uart0: serial@40060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl 146>; + clock-names = "baudclk"; + status = "disabled"; + }; + + gic: gic@44101000 { + compatible = "arm,cortex-a7-gic", "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x44101000 0x1000>, /* Distributer */ + <0x44102000 0x2000>, /* CPU interface */ + <0x44104000 0x2000>, /* Virt interface control */ + <0x44106000 0x2000>; /* Virt CPU interface */ + interrupts = + <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + timer { + compatible = "arm,cortex-a7-timer", + "arm,armv7-timer"; + interrupt-parent = <&gic>; + arm,cpu-registers-not-fw-configured; + always-on; + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +};