From patchwork Wed Jul 11 14:20:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10519949 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BDBC0603D7 for ; Wed, 11 Jul 2018 14:21:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A919229349 for ; Wed, 11 Jul 2018 14:21:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A4A74292EC; Wed, 11 Jul 2018 14:21:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 757F02931E for ; Wed, 11 Jul 2018 14:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388458AbeGKOZp (ORCPT ); Wed, 11 Jul 2018 10:25:45 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:46756 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388480AbeGKOZp (ORCPT ); Wed, 11 Jul 2018 10:25:45 -0400 Received: from ayla.of.borg ([84.194.111.163]) by baptiste.telenet-ops.be with bizsmtp id 9SM61y00X3XaVaC01SM6aC; Wed, 11 Jul 2018 16:21:08 +0200 Received: from rox.of.borg ([192.168.97.57]) by ayla.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fdFzO-0000es-BU; Wed, 11 Jul 2018 16:21:06 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fdFzO-00011e-AP; Wed, 11 Jul 2018 16:21:06 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 01/11] clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider Date: Wed, 11 Jul 2018 16:20:50 +0200 Message-Id: <20180711142100.3765-2-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180711142100.3765-1-geert+renesas@glider.be> References: <20180711142100.3765-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a clock type and macro for defining clocks using the OSC EXTAL predivider combined with a fixed divider. On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and thus must be specified in the configuration structure. Inspired by a patch in the BSP by Takeshi Kihara . Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rcar-gen3-cpg.c | 7 +++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 628b63b85d3f09c5..7533a51c679bfd54 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -563,6 +563,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, return cpg_z_clk_register(core->name, __clk_get_name(parent), base, CPG_FRQCRC_Z2FC_MASK); + case CLK_TYPE_GEN3_OSC: + /* + * Clock combining OSC EXTAL predivider and a fixed divider + */ + div = cpg_pll_config->osc_prediv * core->div; + break; + default: return ERR_PTR(-EINVAL); } diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index ea4f8fc3c4c972e7..d7d84d9e4a1c9c8b 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -23,6 +23,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_PE, CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_Z2, + CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ }; #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ @@ -33,6 +34,8 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ (_parent_sscg) << 16 | (_parent_clean), \ .div = (_div_sscg) << 16 | (_div_clean)) +#define DEF_GEN3_OSC(_name, _id, _parent, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) struct rcar_gen3_cpg_pll_config { u8 extal_div; @@ -40,6 +43,7 @@ struct rcar_gen3_cpg_pll_config { u8 pll1_div; u8 pll3_mult; u8 pll3_div; + u8 osc_prediv; }; #define CPG_RCKCR 0x240