From patchwork Sun Jul 15 20:01:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: saravanan sekar X-Patchwork-Id: 10525135 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C02AC60384 for ; Sun, 15 Jul 2018 20:02:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B439B28911 for ; Sun, 15 Jul 2018 20:02:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A7E0A28944; Sun, 15 Jul 2018 20:02:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D9BE828911 for ; Sun, 15 Jul 2018 20:02:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727328AbeGOU0T (ORCPT ); Sun, 15 Jul 2018 16:26:19 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:46620 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727125AbeGOU0S (ORCPT ); Sun, 15 Jul 2018 16:26:18 -0400 Received: by mail-wr1-f68.google.com with SMTP id s11-v6so29829731wra.13; Sun, 15 Jul 2018 13:02:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LARERkT4kFPnkzoL+I7qvu5ZE6GqgvNe0rJ30yVlxtI=; b=U993ZVfJU2ykusogi7qAEkQIGgsPFEedjhtjhK1Zx2vNS1wYviwmR/wkiGs+8gWAsV I+xftvk/GZy0vEkkxuqPwcbnwvyLthATq1jWEwP38SqXvAypQeh/I6MPXj8yL0hmwVzL tYOCl4H0q65toPRi1TgY8MD8XqrMvojhKP5kW5eATF19p09bE1v9xkvGwwyKnfJGdkWq UXQUHtWYdFMbpgaKddE8yrR5F7Uile1eDbPi/nJrcj0UII+rzCszeQM4i3/NjbQFeUSB ORXJbd93cWfxAPDUDJcWeRTyEZoD126MGYgo7j/v+u8IpzXenG3Le3iftq15W6JXhL/o k2zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LARERkT4kFPnkzoL+I7qvu5ZE6GqgvNe0rJ30yVlxtI=; b=EDgSd0RphTorzU8jUlBcDxj00+AyV8+S3Ud1oSSsahPF+oGf8GG8DdzBMroQIvR5qs /6u8xbWYJjj+9wsdHJoU7i3uNLbp2P5/YhqCKQHozYSBGJTgvQMsNy8Ev/2vHFLg/C8T BG+IURYv16d4w5WqAvjk/X90Sd9507FZ1qQKPMEkWsmxdJuTdKfjgO4sHFRJf0Qw+BU1 Lb5T1thDZd7XEekCcHw7GeuSkqZb0LPhIO6JbL0LH27SUP2qTBXmUJI+eR+hfygj7mr+ pxW9f1smdnnIqfjBBFOwwDFoJeW8ZxNHwv4PzCd309nyrAeN0mMXLa3GliIVZG/FtRTI aQ0w== X-Gm-Message-State: AOUpUlFM8DtbfsWkSWBoqY5EexrHqrbnYX2PAe6J2ObdcdYHcaSn6Hex Q6oGiXg3z9CTOWk84oWTPLU= X-Google-Smtp-Source: AAOMgpepMFCh/sfvwzOgPVVbhTLbNSA1+ythCtqWoWDzFCg+tKMuhDubTrDDqIfoU+KjiBjmcdI3Pw== X-Received: by 2002:adf:9b11:: with SMTP id b17-v6mr10141940wrc.119.1531684936095; Sun, 15 Jul 2018 13:02:16 -0700 (PDT) Received: from parthiban.fritz.box ([62.91.12.240]) by smtp.gmail.com with ESMTPSA id z7-v6sm20816234wrh.85.2018.07.15.13.02.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 15 Jul 2018 13:02:15 -0700 (PDT) From: Saravanan Sekar To: afaerber@suse.de, manivannan.sadhasivam@linaro.org, sboyd@kernel.org Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux@cubietech.com, sravanhome@gmail.com, support@cubietech.com, catalin.marinas@arm.com, mturquette@baylibre.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, thomas.liau@actions-semi.com, darren@cubietech.com, robh+dt@kernel.org, jeff.chen@actions-semi.com, pn@denx.de, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mp-cs@actions-semi.com Subject: [PATCH v5 2/5] dt-bindings: clock: Add S700 support for Actions Semi Soc's Date: Sun, 15 Jul 2018 22:01:48 +0200 Message-Id: <20180715200151.10416-3-sravanhome@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180715200151.10416-1-sravanhome@gmail.com> References: <20180715200151.10416-1-sravanhome@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add clock bindings constants for action S700 Maintain common clock dt-bindings for Actions Semi SoC's S700 and S900. Signed-off-by: Parthiban Nallathambi Signed-off-by: Saravanan Sekar --- ...tions,s900-cmu.txt => actions,owl-cmu.txt} | 20 +-- include/dt-bindings/clock/actions,s700-cmu.h | 118 ++++++++++++++++++ 2 files changed, 129 insertions(+), 9 deletions(-) rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,owl-cmu.txt} (68%) create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt similarity index 68% rename from Documentation/devicetree/bindings/clock/actions,s900-cmu.txt rename to Documentation/devicetree/bindings/clock/actions,owl-cmu.txt index 93e4fb827cd6..d1e60d297387 100644 --- a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt +++ b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt @@ -1,12 +1,14 @@ -* Actions S900 Clock Management Unit (CMU) +* Actions Semi Owl Clock Management Unit (CMU) -The Actions S900 clock management unit generates and supplies clock to various -controllers within the SoC. The clock binding described here is applicable to -S900 SoC. +The Actions Semi Owl Clock Management Unit generates and supplies clock +to various controllers within the SoC. The clock binding described here is +applicable to S900 and S700 SoC's. Required Properties: -- compatible: should be "actions,s900-cmu" +- compatible: should be one of the following, + "actions,s900-cmu" + "actions,s700-cmu" - reg: physical base address of the controller and length of memory mapped region. - clocks: Reference to the parent clocks ("hosc", "losc") @@ -15,16 +17,16 @@ Required Properties: Each clock is assigned an identifier, and client nodes can use this identifier to specify the clock which they consume. -All available clocks are defined as preprocessor macros in -dt-bindings/clock/actions,s900-cmu.h header and can be used in device -tree sources. +All available clocks are defined as preprocessor macros in corresponding +dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be +used in device tree sources. External clocks: The hosc clock used as input for the plls is generated outside the SoC. It is expected that it is defined using standard clock bindings as "hosc". -Actions S900 CMU also requires one more clock: +Actions Semi S900 CMU also requires one more clock: - "losc" - internal low frequency oscillator Example: Clock Management Unit node: diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h new file mode 100644 index 000000000000..3e1942996724 --- /dev/null +++ b/include/dt-bindings/clock/actions,s700-cmu.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Device Tree binding constants for Actions Semi S700 Clock Management Unit + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu + * + * Author: Pathiban Nallathambi + * Author: Saravanan Sekar + */ + +#ifndef __DT_BINDINGS_CLOCK_S700_H +#define __DT_BINDINGS_CLOCK_S700_H + +#define CLK_NONE 0 + +/* pll clocks */ +#define CLK_CORE_PLL 1 +#define CLK_DEV_PLL 2 +#define CLK_DDR_PLL 3 +#define CLK_NAND_PLL 4 +#define CLK_DISPLAY_PLL 5 +#define CLK_TVOUT_PLL 6 +#define CLK_CVBS_PLL 7 +#define CLK_AUDIO_PLL 8 +#define CLK_ETHERNET_PLL 9 + +/* system clock */ +#define CLK_CPU 10 +#define CLK_DEV 11 +#define CLK_AHB 12 +#define CLK_APB 13 +#define CLK_DMAC 14 +#define CLK_NOC0_CLK_MUX 15 +#define CLK_NOC1_CLK_MUX 16 +#define CLK_HP_CLK_MUX 17 +#define CLK_HP_CLK_DIV 18 +#define CLK_NOC1_CLK_DIV 19 +#define CLK_NOC0 20 +#define CLK_NOC1 21 +#define CLK_SENOR_SRC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 +#define CLK_TIMER 24 +#define CLK_DSI 25 +#define CLK_CSI 26 +#define CLK_SI 27 +#define CLK_DE 28 +#define CLK_HDE 29 +#define CLK_VDE 30 +#define CLK_VCE 31 +#define CLK_NAND 32 +#define CLK_SD0 33 +#define CLK_SD1 34 +#define CLK_SD2 35 + +#define CLK_UART0 36 +#define CLK_UART1 37 +#define CLK_UART2 38 +#define CLK_UART3 39 +#define CLK_UART4 40 +#define CLK_UART5 41 +#define CLK_UART6 42 + +#define CLK_PWM0 43 +#define CLK_PWM1 44 +#define CLK_PWM2 45 +#define CLK_PWM3 46 +#define CLK_PWM4 47 +#define CLK_PWM5 48 +#define CLK_GPU3D 49 + +#define CLK_I2C0 50 +#define CLK_I2C1 51 +#define CLK_I2C2 52 +#define CLK_I2C3 53 + +#define CLK_SPI0 54 +#define CLK_SPI1 55 +#define CLK_SPI2 56 +#define CLK_SPI3 57 + +#define CLK_USB3_480MPLL0 58 +#define CLK_USB3_480MPHY0 59 +#define CLK_USB3_5GPHY 60 +#define CLK_USB3_CCE 61 +#define CLK_USB3_MAC 62 + +#define CLK_LCD 63 +#define CLK_HDMI_AUDIO 64 +#define CLK_I2SRX 65 +#define CLK_I2STX 66 + +#define CLK_SENSOR0 67 +#define CLK_SENSOR1 68 + +#define CLK_HDMI_DEV 69 + +#define CLK_ETHERNET 70 +#define CLK_RMII_REF 71 + +#define CLK_USB2H0_PLLEN 72 +#define CLK_USB2H0_PHY 73 +#define CLK_USB2H0_CCE 74 +#define CLK_USB2H1_PLLEN 75 +#define CLK_USB2H1_PHY 76 +#define CLK_USB2H1_CCE 77 + +#define CLK_TVOUT 78 + +#define CLK_THERMAL_SENSOR 79 + +#define CLK_IRC_SWITCH 80 +#define CLK_PCM1 81 +#define CLK_NR_CLKS (CLK_PCM1 + 1) + +#endif /* __DT_BINDINGS_CLOCK_S700_H */