From patchwork Fri Jul 20 13:45:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 10537531 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 92163602CA for ; Fri, 20 Jul 2018 13:46:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8977B297C1 for ; Fri, 20 Jul 2018 13:46:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7DF3C297C9; Fri, 20 Jul 2018 13:46:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 24646297C1 for ; Fri, 20 Jul 2018 13:46:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732807AbeGTOe3 (ORCPT ); Fri, 20 Jul 2018 10:34:29 -0400 Received: from imap1.codethink.co.uk ([176.9.8.82]:36147 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731608AbeGTOd7 (ORCPT ); Fri, 20 Jul 2018 10:33:59 -0400 Received: from [148.252.241.226] (helo=rainbowdash) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1fgViw-0000P5-CD; Fri, 20 Jul 2018 14:45:34 +0100 Received: from ben by rainbowdash with local (Exim 4.91) (envelope-from ) id 1fgViw-0003SA-1x; Fri, 20 Jul 2018 14:45:34 +0100 From: Ben Dooks To: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, jonathanh@nvidia.co, thierry.reding@gmail.com, linux-kernel@lists.codethink.co.uk, Ben Dooks Subject: [PATCH 5/8] clk: tegra: add mux-only clock option Date: Fri, 20 Jul 2018 14:45:29 +0100 Message-Id: <20180720134532.13148-6-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180720134532.13148-1-ben.dooks@codethink.co.uk> References: <20180720134532.13148-1-ben.dooks@codethink.co.uk> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If both the TEGRA_PERIPH_NO_DIV and TEGRA_PERIPH_NO_GATE are set as the clock is a mux only, then the clock code fails as it does not handle both these at the same time. Add support for this by adding new ops with just the parent get/set. This is required to add the 2d and 3d idle clocks. Signed-off-by: Ben Dooks --- drivers/clk/tegra/clk-periph.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 9475c00b7cf9..0c377d2dac43 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -137,6 +137,11 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = { .set_rate = clk_periph_set_rate, }; +static const struct clk_ops tegra_clk_periph_nodivgate_ops = { + .get_parent = clk_periph_get_parent, + .set_parent = clk_periph_set_parent, +}; + static struct clk *_tegra_clk_register_periph(const char *name, const char * const *parent_names, int num_parents, struct tegra_clk_periph *periph, @@ -147,8 +152,11 @@ static struct clk *_tegra_clk_register_periph(const char *name, struct clk_init_data init; const struct tegra_clk_periph_regs *bank; bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); + bool gate = !(periph->gate.flags & TEGRA_PERIPH_NO_GATE); - if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) { + if (!div && !gate) + init.ops = &tegra_clk_periph_nodivgate_ops; + else if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) { flags |= CLK_SET_RATE_PARENT; init.ops = &tegra_clk_periph_nodiv_ops; } else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE) @@ -171,7 +179,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, periph->mux.reg = clk_base + offset; periph->divider.reg = div ? (clk_base + offset) : NULL; periph->gate.clk_base = clk_base; - periph->gate.regs = bank; + periph->gate.regs = gate ? bank : NULL; periph->gate.enable_refcnt = periph_clk_enb_refcnt; clk = clk_register(NULL, &periph->hw); @@ -180,7 +188,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, periph->mux.hw.clk = clk; periph->divider.hw.clk = div ? clk : NULL; - periph->gate.hw.clk = clk; + periph->gate.hw.clk = gate ? clk : NULL; return clk; }