From patchwork Thu Jul 26 15:35:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546061 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5340BA661 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 438192B6E0 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 40DFF2B7BA; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B9E252B76D for ; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731730AbeGZQwr (ORCPT ); Thu, 26 Jul 2018 12:52:47 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:45344 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731784AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by baptiste.telenet-ops.be with bizsmtp id FTbN1y00B3XaVaC01TbN9c; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008UW-3o; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002co-2d; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 05/11] clk: renesas: r8a77980: Add OSC predivider configuration and clock Date: Thu, 26 Jul 2018 17:35:11 +0200 Message-Id: <20180726153517.10020-6-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC clock. Hence augment the configuration structure with all documented predivider values. Add the OSC clock using the configured predivider. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Fix predivider for 27 MHz EXTAL (table under Table 8.2e wrongly uses 25 MHz). --- drivers/clk/renesas/r8a77980-cpg-mssr.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index d7ebd9ec00594fc8..a8b8d8613b46dd3c 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -96,6 +96,8 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014), + + DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8), }; static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { @@ -171,23 +173,23 @@ static const unsigned int r8a77980_crit_mod_clks[] __initconst = { */ /* - * MD EXTAL PLL2 PLL1 PLL3 + * MD EXTAL PLL2 PLL1 PLL3 OSC * 14 13 (MHz) - * -------------------------------------------------- - * 0 0 16.66 x 1 x240 x192 x192 - * 0 1 20 x 1 x200 x160 x160 - * 1 0 27 x 1 x148 x118 x118 - * 1 1 33.33 / 2 x240 x192 x192 + * -------------------------------------------------------- + * 0 0 16.66 x 1 x240 x192 x192 /16 + * 0 1 20 x 1 x200 x160 x160 /19 + * 1 0 27 x 1 x148 x118 x118 /26 + * 1 1 33.33 / 2 x240 x192 x192 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = { - /* EXTAL div PLL1 mult/div PLL3 mult/div */ - { 1, 192, 1, 192, 1, }, - { 1, 160, 1, 160, 1, }, - { 1, 118, 1, 118, 1, }, - { 2, 192, 1, 192, 1, }, + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ + { 1, 192, 1, 192, 1, 16, }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 118, 1, 118, 1, 26, }, + { 2, 192, 1, 192, 1, 32, }, }; static int __init r8a77980_cpg_mssr_init(struct device *dev)