From patchwork Wed Aug 1 08:19:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 10551833 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DEA2A14E2 for ; Wed, 1 Aug 2018 08:19:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CFEFF2AEC4 for ; Wed, 1 Aug 2018 08:19:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C26D92AE86; Wed, 1 Aug 2018 08:19:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E32132AE86 for ; Wed, 1 Aug 2018 08:19:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388353AbeHAKE1 (ORCPT ); Wed, 1 Aug 2018 06:04:27 -0400 Received: from mail.bootlin.com ([62.4.15.54]:33878 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388304AbeHAKE1 (ORCPT ); Wed, 1 Aug 2018 06:04:27 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id AF02F20799; Wed, 1 Aug 2018 10:19:53 +0200 (CEST) Received: from localhost.localdomain (AAubervilliers-681-1-89-120.w90-88.abo.wanadoo.fr [90.88.30.120]) by mail.bootlin.com (Postfix) with ESMTPSA id 57BA62074F; Wed, 1 Aug 2018 10:19:53 +0200 (CEST) From: Boris Brezillon To: Mike Turquette , Stephen Boyd , linux-clk@vger.kernel.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org, Julien Su , Mason Yang , , linux-arm-kernel@lists.infradead.org, Michal Simek , Boris Brezillon Subject: [PATCH 2/2] dt-bindings: clock: Add bindings for the Clocking Wizard IP Date: Wed, 1 Aug 2018 10:19:50 +0200 Message-Id: <20180801081950.10497-2-boris.brezillon@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180801081950.10497-1-boris.brezillon@bootlin.com> References: <20180801081950.10497-1-boris.brezillon@bootlin.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document Xilinx Clocking Wizard bindings. Signed-off-by: Boris Brezillon Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/xlnx,clk-wizard.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clk-wizard.txt diff --git a/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.txt b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.txt new file mode 100644 index 000000000000..1bf7a764f4a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.txt @@ -0,0 +1,28 @@ +Device Tree Clock bindings for the "Clocking Wizard" IP provided by Xilinx + +This block can be used to generate up to 4 clock signals out of a single input +clock. It embeds a PLL to generate an intermediate clock which then feeds 4 +clock dividers whose divider value can be adjusted based on the user needs. + +Required properties: + - #clock-cells: must be 1. The cell is encoding the id of the output clk + (from 0 to xlnx,clk-wizard-num-outputs - 1) + - compatible: must be "xlnx,clk-wizard-5.1" + - clocks: 2 clocks are required + - clock-names: should contain 2 clock names: "aclk" and "clkin". + "aclk" is driving the register interface and "clk_in" is the + input clock signal that is used by the PLL block + - xlnx,clk-wizard-num-outputs: this describe the number of output clocks + (chosen at synthesization time) + - reg: registers used to configure the Clocking wizard block + +Example: + + clkwizard: clkwizard@43c20000 { + compatible = "xlnx,clk-wizard-5.1"; + reg = <0x43c20000 0x10000>; + clocks = <&clkc 18>, <&clkc 18>; + clock-names = "aclk", "clk_in1"; + #clock-cells = <1>; + xlnx,clk-wizard-num-outputs = <2>; + };