| Message ID | 20180803030237.3366-2-songjun.wu@linux.intel.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | MIPS: intel: add initial support for Intel MIPS SoCs | expand |
Hi Songjun / Hua, On Fri, Aug 03, 2018 at 11:02:20AM +0800, Songjun Wu wrote: > From: Hua Ma <hua.ma@linux.intel.com> > > Add initial support for Intel MIPS interAptiv SoCs made by Intel. > This series will add support for the grx500 family. > > The series allows booting a minimal system using a initramfs. Thanks for submitting this - I have some comments below. > diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms > index ac7ad54f984f..bcd647060f3e 100644 > --- a/arch/mips/Kbuild.platforms > +++ b/arch/mips/Kbuild.platforms > @@ -12,6 +12,7 @@ platforms += cobalt > platforms += dec > platforms += emma > platforms += generic > +platforms += intel-mips > platforms += jazz > platforms += jz4740 > platforms += lantiq Oh EVA, why must you ruin nice things... Ideally I'd be suggesting that we use the generic platform but it doesn't yet have a nice way to deal with non-standard EVA setups. It would be good if we could make sure that's the only reason for your custom platform though, so that once generic does support EVA we can migrate your system over. Most notably, it would be good to make use of the UHI-specified boot protocol if possible (ie. $r4==-2, $r5==&dtb). It looks like your prom_init_cmdline() supports multiple boot protocols - could you clarify which is actually used? > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 08c10c518f83..2d34f17f3e24 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -409,6 +409,34 @@ config LANTIQ > select ARCH_HAS_RESET_CONTROLLER > select RESET_CONTROLLER > > +config INTEL_MIPS > + bool "Intel MIPS interAptiv SoC based platforms" > + select BOOT_RAW > + select CEVT_R4K > + select COMMON_CLK > + select CPU_MIPS32_3_5_EVA > + select CPU_MIPS32_3_5_FEATURES > + select CPU_MIPSR2_IRQ_EI > + select CPU_MIPSR2_IRQ_VI > + select CSRC_R4K > + select DMA_NONCOHERENT > + select GENERIC_ISA_DMA > + select IRQ_MIPS_CPU > + select MFD_CORE > + select MFD_SYSCON > + select MIPS_CPU_SCACHE > + select MIPS_GIC > + select SYS_HAS_CPU_MIPS32_R1 For a system based on interAptiv you should never need to build a MIPS32r1 kernel, so you should remove the above select. > diff --git a/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h b/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h > new file mode 100644 > index 000000000000..ac5f3b943d2a > --- /dev/null > +++ b/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h > @@ -0,0 +1,61 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * This file was derived from: include/asm-mips/cpu-features.h > + * Copyright (C) 2003, 2004 Ralf Baechle > + * Copyright (C) 2004 Maciej W. Rozycki > + * Copyright (C) 2018 Intel Corporation. > + */ > + > +#ifndef __ASM_MACH_INTEL_MIPS_CPU_FEATURE_OVERRIDES_H > +#define __ASM_MACH_INTEL_MIPS_CPU_FEATURE_OVERRIDES_H > + > +#define cpu_has_tlb 1 > +#define cpu_has_4kex 1 > +#define cpu_has_3k_cache 0 > +#define cpu_has_4k_cache 1 > +#define cpu_has_tx39_cache 0 > +#define cpu_has_sb1_cache 0 > +#define cpu_has_fpu 0 > +#define cpu_has_32fpr 0 > +#define cpu_has_counter 1 > +#define cpu_has_watch 1 > +#define cpu_has_divec 1 > + > +#define cpu_has_prefetch 1 > +#define cpu_has_ejtag 1 > +#define cpu_has_llsc 1 > + > +#define cpu_has_mips16 0 > +#define cpu_has_mdmx 0 > +#define cpu_has_mips3d 0 > +#define cpu_has_smartmips 0 > +#define cpu_has_mmips 0 > +#define cpu_has_vz 0 > + > +#define cpu_has_mips32r1 1 > +#define cpu_has_mips32r2 1 > +#define cpu_has_mips64r1 0 > +#define cpu_has_mips64r2 0 > + > +#define cpu_has_dsp 1 > +#define cpu_has_dsp2 0 > +#define cpu_has_mipsmt 1 > + > +#define cpu_has_vint 1 > +#define cpu_has_veic 0 > + > +#define cpu_has_64bits 0 > +#define cpu_has_64bit_zero_reg 0 > +#define cpu_has_64bit_gp_regs 0 > +#define cpu_has_64bit_addresses 0 > + > +#define cpu_has_cm2 1 > +#define cpu_has_cm2_l2sync 1 > +#define cpu_has_eva 1 > +#define cpu_has_tlbinv 1 > + > +#define cpu_dcache_line_size() 32 > +#define cpu_icache_line_size() 32 > +#define cpu_scache_line_size() 32 If you rebase atop linux-next or mips-next then you should find that many of these defines are now redundant, especially after removing the SYS_HAS_CPU_MIPS32_R1 select which means your kernel build will always target MIPS32r2. Due to architectural restrictions on where various options can be present, you should be able to remove: - cpu_has_4kex - cpu_has_3k_cache - cpu_has_4k_cache - cpu_has_32fpr - cpu_has_divec - cpu_has_prefetch - cpu_has_llsc cpu_has_mmips defaults to a compile-time zero unless you select CONFIG_SYS_SUPPORTS_MICROMIPS, so please remove that one. cpu_has_64bit_gp_regs & cpu_has_64bit_addresses both default to zero already for 32bit kernel builds, so please remove those. cpu_has_cm2 & cpu_has_cm2_l2sync don't exist anywhere in-tree, so please remove those. Additionally cpu_has_sb1_cache is not used anywhere, or defined by asm/cpu-features.h & seems to just be left over in some platform override files including presumably one you based yours on. Please remove it too. Also you select CPU_MIPSR2_IRQ_EI but define cpu_has_veic as 0, could you check that mismatch? > diff --git a/arch/mips/include/asm/mach-intel-mips/irq.h b/arch/mips/include/asm/mach-intel-mips/irq.h > new file mode 100644 > index 000000000000..12a949084856 > --- /dev/null > +++ b/arch/mips/include/asm/mach-intel-mips/irq.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2014 Lei Chuanhua <Chuanhua.lei@lantiq.com> > + * Copyright (C) 2018 Intel Corporation. > + */ > + > +#ifndef __INTEL_MIPS_IRQ_H > +#define __INTEL_MIPS_IRQ_H > + > +#define MIPS_CPU_IRQ_BASE 0 > +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) These 2 defines are the defaults anyway, so please remove them. > +#define NR_IRQS 256 And if you don't actually need this then you could remove irq.h entirely - do you actually use more than 128 IRQs? > diff --git a/arch/mips/include/asm/mach-intel-mips/spaces.h b/arch/mips/include/asm/mach-intel-mips/spaces.h > new file mode 100644 > index 000000000000..80e7b09f712c > --- /dev/null > +++ b/arch/mips/include/asm/mach-intel-mips/spaces.h >% >% >% > +#define IO_SIZE _AC(0x10000000, UL) > +#define IO_SHIFT _AC(0x10000000, UL) These IO_ defines don't appear to be used anywhere? > +/* IO space one */ > +#define __pa_symbol(x) __pa(x) Can you explain why you need this, rather than the default definition of __pa_symbol()? The comment doesn't seem to describe much of anything. > diff --git a/arch/mips/include/asm/mach-intel-mips/war.h b/arch/mips/include/asm/mach-intel-mips/war.h > new file mode 100644 > index 000000000000..1c95553151e1 > --- /dev/null > +++ b/arch/mips/include/asm/mach-intel-mips/war.h > @@ -0,0 +1,18 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_MIPS_MACH_INTEL_MIPS_WAR_H > +#define __ASM_MIPS_MACH_INTEL_MIPS_WAR_H > + > +#define R4600_V1_INDEX_ICACHEOP_WAR 0 > +#define R4600_V1_HIT_CACHEOP_WAR 0 > +#define R4600_V2_HIT_CACHEOP_WAR 0 > +#define R5432_CP0_INTERRUPT_WAR 0 > +#define BCM1250_M3_WAR 0 > +#define SIBYTE_1956_WAR 0 > +#define MIPS4K_ICACHE_REFILL_WAR 0 > +#define MIPS_CACHE_SYNC_WAR 0 > +#define TX49XX_ICACHE_INDEX_INV_WAR 0 > +#define ICACHE_REFILLS_WORKAROUND_WAR 0 > +#define R10000_LLSC_WAR 0 > +#define MIPS34K_MISSED_ITLB_WAR 0 > + > +#endif /* __ASM_MIPS_MACH_INTEL_MIPS_WAR_H */ Since you need none of these workarounds, you shouldn't need war.h at all. > diff --git a/arch/mips/intel-mips/Kconfig b/arch/mips/intel-mips/Kconfig > new file mode 100644 > index 000000000000..35d2ae2b5408 > --- /dev/null > +++ b/arch/mips/intel-mips/Kconfig > @@ -0,0 +1,22 @@ > +if INTEL_MIPS > + > +choice > + prompt "Built-in device tree" > + help > + Legacy bootloaders do not pass a DTB pointer to the kernel, so > + if a "wrapper" is not being used, the kernel will need to include > + a device tree that matches the target board. > + > + The builtin DTB will only be used if the firmware does not supply > + a valid DTB. > + > +config DTB_INTEL_MIPS_NONE > + bool "None" > + > +config DTB_INTEL_MIPS_GRX500 > + bool "Intel MIPS GRX500 Board" > + select BUILTIN_DTB > + > +endchoice > + > +endif So do you actually have both styles of bootloader? > diff --git a/arch/mips/intel-mips/prom.c b/arch/mips/intel-mips/prom.c > new file mode 100644 > index 000000000000..a1b1393c13bc > --- /dev/null > +++ b/arch/mips/intel-mips/prom.c >% >% >% > +static void __init prom_init_cmdline(void) > +{ > + int i; > + int argc; > + char **argv; > + > + /* > + * If u-boot pass parameters, it is ok, however, if without u-boot > + * JTAG or other tool has to reset all register value before it goes > + * emulation most likely belongs to this category > + */ > + if (fw_arg0 == 0 || fw_arg1 == 0) > + return; I don't understand what you're trying to say here, or why this check exists. If you boot with fw_arg0 == fw_arg1 == 0 then you'd just hit the loop below right, and execute zero iterations of it? That seems like it would be fine without this special case. > + /* > + * a0: fw_arg0 - the number of string in init cmdline > + * a1: fw_arg1 - the address of string in init cmdline > + * > + * In accordance with the MIPS UHI specification, > + * the bootloader can pass the following arguments to the kernel: > + * - $a0: -2. > + * - $a1: KSEG0 address of the flattened device-tree blob. > + */ > + if (fw_arg0 == -2) > + return; > + > + argc = fw_arg0; > + argv = (char **)KSEG1ADDR(fw_arg1); > + > + arcs_cmdline[0] = '\0'; > + > + for (i = 0; i < argc; i++) { > + char *p = (char *)KSEG1ADDR(argv[i]); > + > + if (argv[i] && *p) { > + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); > + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); > + } > + } Why do you need to use kseg1? Why can't the arguments be accessed cached? Are the arguments passed as virtual or physical addresses? If virtual & we can access them cached then you could replace all of this with a call to fw_init_cmdline(). > +static int __init plat_enable_iocoherency(void) > +{ > + if (!mips_cps_numiocu(0)) > + return 0; > + > + /* Nothing special needs to be done to enable coherency */ > + pr_info("Coherence Manager IOCU detected\n"); > + /* Second IOCU for MPE or other master access register */ > + write_gcr_reg0_base(0xa0000000); > + write_gcr_reg0_mask(0xf8000000 | CM_GCR_REGn_MASK_CMTGT_IOCU1); > + return 1; > +} > + > +static void __init plat_setup_iocoherency(void) > +{ > + if (plat_enable_iocoherency() && > + coherentio == IO_COHERENCE_DISABLED) { > + pr_info("Hardware DMA cache coherency disabled\n"); > + return; > + } > + panic("This kind of IO coherency is not supported!"); > +} Since you select CONFIG_DMA_NONCOHERENT in Kconfig, coherentio will always equal IO_COHERENCE_DISABLED. That suggests to me that the above 2 functions are probably useless, or at least needlessly convoluted. > +static int __init plat_publish_devices(void) > +{ > + if (!of_have_populated_dt()) > + return 0; > + return of_platform_populate(NULL, of_default_bus_match_table, NULL, > + NULL); > +} > +arch_initcall(plat_publish_devices); The core DT code calls of_platform_populate() already (see of_platform_default_populate_init()), so you can remove this function. Thanks, Paul -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 8/4/2018 1:49 AM, Paul Burton wrote: > Hi Songjun / Hua, > > On Fri, Aug 03, 2018 at 11:02:20AM +0800, Songjun Wu wrote: >> From: Hua Ma <hua.ma@linux.intel.com> >> >> Add initial support for Intel MIPS interAptiv SoCs made by Intel. >> This series will add support for the grx500 family. >> >> The series allows booting a minimal system using a initramfs. > Thanks for submitting this - I have some comments below. Thanks for the review. >> diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms >> index ac7ad54f984f..bcd647060f3e 100644 >> --- a/arch/mips/Kbuild.platforms >> +++ b/arch/mips/Kbuild.platforms >> @@ -12,6 +12,7 @@ platforms += cobalt >> platforms += dec >> platforms += emma >> platforms += generic >> +platforms += intel-mips >> platforms += jazz >> platforms += jz4740 >> platforms += lantiq > Oh EVA, why must you ruin nice things... Ideally I'd be suggesting that > we use the generic platform but it doesn't yet have a nice way to deal > with non-standard EVA setups. yes, we only support EVA. > It would be good if we could make sure that's the only reason for your > custom platform though, so that once generic does support EVA we can > migrate your system over. Most notably, it would be good to make use of > the UHI-specified boot protocol if possible (ie. $r4==-2, $r5==&dtb). > > It looks like your prom_init_cmdline() supports multiple boot protocols > - could you clarify which is actually used? this patch only support build-in dts, we will do a clean up. >> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig >> index 08c10c518f83..2d34f17f3e24 100644 >> --- a/arch/mips/Kconfig >> +++ b/arch/mips/Kconfig >> @@ -409,6 +409,34 @@ config LANTIQ >> select ARCH_HAS_RESET_CONTROLLER >> select RESET_CONTROLLER >> >> +config INTEL_MIPS >> + bool "Intel MIPS interAptiv SoC based platforms" >> + select BOOT_RAW >> + select CEVT_R4K >> + select COMMON_CLK >> + select CPU_MIPS32_3_5_EVA >> + select CPU_MIPS32_3_5_FEATURES >> + select CPU_MIPSR2_IRQ_EI >> + select CPU_MIPSR2_IRQ_VI >> + select CSRC_R4K >> + select DMA_NONCOHERENT >> + select GENERIC_ISA_DMA >> + select IRQ_MIPS_CPU >> + select MFD_CORE >> + select MFD_SYSCON >> + select MIPS_CPU_SCACHE >> + select MIPS_GIC >> + select SYS_HAS_CPU_MIPS32_R1 > For a system based on interAptiv you should never need to build a > MIPS32r1 kernel, so you should remove the above select. will remove. >> diff --git a/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h b/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h >> new file mode 100644 >> index 000000000000..ac5f3b943d2a >> --- /dev/null >> +++ b/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h >> @@ -0,0 +1,61 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * This file was derived from: include/asm-mips/cpu-features.h >> + * Copyright (C) 2003, 2004 Ralf Baechle >> + * Copyright (C) 2004 Maciej W. Rozycki >> + * Copyright (C) 2018 Intel Corporation. >> + */ >> + >> +#ifndef __ASM_MACH_INTEL_MIPS_CPU_FEATURE_OVERRIDES_H >> +#define __ASM_MACH_INTEL_MIPS_CPU_FEATURE_OVERRIDES_H >> + >> +#define cpu_has_tlb 1 >> +#define cpu_has_4kex 1 >> +#define cpu_has_3k_cache 0 >> +#define cpu_has_4k_cache 1 >> +#define cpu_has_tx39_cache 0 >> +#define cpu_has_sb1_cache 0 >> +#define cpu_has_fpu 0 >> +#define cpu_has_32fpr 0 >> +#define cpu_has_counter 1 >> +#define cpu_has_watch 1 >> +#define cpu_has_divec 1 >> + >> +#define cpu_has_prefetch 1 >> +#define cpu_has_ejtag 1 >> +#define cpu_has_llsc 1 >> + >> +#define cpu_has_mips16 0 >> +#define cpu_has_mdmx 0 >> +#define cpu_has_mips3d 0 >> +#define cpu_has_smartmips 0 >> +#define cpu_has_mmips 0 >> +#define cpu_has_vz 0 >> + >> +#define cpu_has_mips32r1 1 >> +#define cpu_has_mips32r2 1 >> +#define cpu_has_mips64r1 0 >> +#define cpu_has_mips64r2 0 >> + >> +#define cpu_has_dsp 1 >> +#define cpu_has_dsp2 0 >> +#define cpu_has_mipsmt 1 >> + >> +#define cpu_has_vint 1 >> +#define cpu_has_veic 0 >> + >> +#define cpu_has_64bits 0 >> +#define cpu_has_64bit_zero_reg 0 >> +#define cpu_has_64bit_gp_regs 0 >> +#define cpu_has_64bit_addresses 0 >> + >> +#define cpu_has_cm2 1 >> +#define cpu_has_cm2_l2sync 1 >> +#define cpu_has_eva 1 >> +#define cpu_has_tlbinv 1 >> + >> +#define cpu_dcache_line_size() 32 >> +#define cpu_icache_line_size() 32 >> +#define cpu_scache_line_size() 32 > If you rebase atop linux-next or mips-next then you should find that > many of these defines are now redundant, especially after removing the > SYS_HAS_CPU_MIPS32_R1 select which means your kernel build will always > target MIPS32r2. > > Due to architectural restrictions on where various options can be > present, you should be able to remove: > > - cpu_has_4kex > - cpu_has_3k_cache > - cpu_has_4k_cache > - cpu_has_32fpr > - cpu_has_divec > - cpu_has_prefetch > - cpu_has_llsc > > cpu_has_mmips defaults to a compile-time zero unless you select > CONFIG_SYS_SUPPORTS_MICROMIPS, so please remove that one. > > cpu_has_64bit_gp_regs & cpu_has_64bit_addresses both default to zero > already for 32bit kernel builds, so please remove those. > > cpu_has_cm2 & cpu_has_cm2_l2sync don't exist anywhere in-tree, so please > remove those. > > Additionally cpu_has_sb1_cache is not used anywhere, or defined by > asm/cpu-features.h & seems to just be left over in some platform > override files including presumably one you based yours on. Please > remove it too. Thanks, will remove. > Also you select CPU_MIPSR2_IRQ_EI but define cpu_has_veic as 0, could > you check that mismatch? The hardware does support, but the software does not support. >> diff --git a/arch/mips/include/asm/mach-intel-mips/irq.h b/arch/mips/include/asm/mach-intel-mips/irq.h >> new file mode 100644 >> index 000000000000..12a949084856 >> --- /dev/null >> +++ b/arch/mips/include/asm/mach-intel-mips/irq.h >> @@ -0,0 +1,17 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Copyright (C) 2014 Lei Chuanhua <Chuanhua.lei@lantiq.com> >> + * Copyright (C) 2018 Intel Corporation. >> + */ >> + >> +#ifndef __INTEL_MIPS_IRQ_H >> +#define __INTEL_MIPS_IRQ_H >> + >> +#define MIPS_CPU_IRQ_BASE 0 >> +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) > These 2 defines are the defaults anyway, so please remove them. Thanks, will remove. >> +#define NR_IRQS 256 > And if you don't actually need this then you could remove irq.h entirely > - do you actually use more than 128 IRQs? Yes, the hardware support 256 IRQs. >> diff --git a/arch/mips/include/asm/mach-intel-mips/spaces.h b/arch/mips/include/asm/mach-intel-mips/spaces.h >> new file mode 100644 >> index 000000000000..80e7b09f712c >> --- /dev/null >> +++ b/arch/mips/include/asm/mach-intel-mips/spaces.h >> % >% >% >> +#define IO_SIZE _AC(0x10000000, UL) >> +#define IO_SHIFT _AC(0x10000000, UL) > These IO_ defines don't appear to be used anywhere? Thanks, will remove. >> +/* IO space one */ >> +#define __pa_symbol(x) __pa(x) > Can you explain why you need this, rather than the default definition of > __pa_symbol()? The comment doesn't seem to describe much of anything. Thanks, will remove. >> diff --git a/arch/mips/include/asm/mach-intel-mips/war.h b/arch/mips/include/asm/mach-intel-mips/war.h >> new file mode 100644 >> index 000000000000..1c95553151e1 >> --- /dev/null >> +++ b/arch/mips/include/asm/mach-intel-mips/war.h >> @@ -0,0 +1,18 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +#ifndef __ASM_MIPS_MACH_INTEL_MIPS_WAR_H >> +#define __ASM_MIPS_MACH_INTEL_MIPS_WAR_H >> + >> +#define R4600_V1_INDEX_ICACHEOP_WAR 0 >> +#define R4600_V1_HIT_CACHEOP_WAR 0 >> +#define R4600_V2_HIT_CACHEOP_WAR 0 >> +#define R5432_CP0_INTERRUPT_WAR 0 >> +#define BCM1250_M3_WAR 0 >> +#define SIBYTE_1956_WAR 0 >> +#define MIPS4K_ICACHE_REFILL_WAR 0 >> +#define MIPS_CACHE_SYNC_WAR 0 >> +#define TX49XX_ICACHE_INDEX_INV_WAR 0 >> +#define ICACHE_REFILLS_WORKAROUND_WAR 0 >> +#define R10000_LLSC_WAR 0 >> +#define MIPS34K_MISSED_ITLB_WAR 0 >> + >> +#endif /* __ASM_MIPS_MACH_INTEL_MIPS_WAR_H */ > Since you need none of these workarounds, you shouldn't need war.h at > all. Thanks, will remove this file. >> diff --git a/arch/mips/intel-mips/Kconfig b/arch/mips/intel-mips/Kconfig >> new file mode 100644 >> index 000000000000..35d2ae2b5408 >> --- /dev/null >> +++ b/arch/mips/intel-mips/Kconfig >> @@ -0,0 +1,22 @@ >> +if INTEL_MIPS >> + >> +choice >> + prompt "Built-in device tree" >> + help >> + Legacy bootloaders do not pass a DTB pointer to the kernel, so >> + if a "wrapper" is not being used, the kernel will need to include >> + a device tree that matches the target board. >> + >> + The builtin DTB will only be used if the firmware does not supply >> + a valid DTB. >> + >> +config DTB_INTEL_MIPS_NONE >> + bool "None" >> + >> +config DTB_INTEL_MIPS_GRX500 >> + bool "Intel MIPS GRX500 Board" >> + select BUILTIN_DTB >> + >> +endchoice >> + >> +endif > So do you actually have both styles of bootloader? this patch only support the build-in, will do a clean up. >> diff --git a/arch/mips/intel-mips/prom.c b/arch/mips/intel-mips/prom.c >> new file mode 100644 >> index 000000000000..a1b1393c13bc >> --- /dev/null >> +++ b/arch/mips/intel-mips/prom.c >> % >% >% >> +static void __init prom_init_cmdline(void) >> +{ >> + int i; >> + int argc; >> + char **argv; >> + >> + /* >> + * If u-boot pass parameters, it is ok, however, if without u-boot >> + * JTAG or other tool has to reset all register value before it goes >> + * emulation most likely belongs to this category >> + */ >> + if (fw_arg0 == 0 || fw_arg1 == 0) >> + return; > I don't understand what you're trying to say here, or why this check > exists. If you boot with fw_arg0 == fw_arg1 == 0 then you'd just hit the > loop below right, and execute zero iterations of it? That seems like it > would be fine without this special case. this patch do not support this , will remove. >> + /* >> + * a0: fw_arg0 - the number of string in init cmdline >> + * a1: fw_arg1 - the address of string in init cmdline >> + * >> + * In accordance with the MIPS UHI specification, >> + * the bootloader can pass the following arguments to the kernel: >> + * - $a0: -2. >> + * - $a1: KSEG0 address of the flattened device-tree blob. >> + */ >> + if (fw_arg0 == -2) >> + return; >> + >> + argc = fw_arg0; >> + argv = (char **)KSEG1ADDR(fw_arg1); >> + >> + arcs_cmdline[0] = '\0'; >> + >> + for (i = 0; i < argc; i++) { >> + char *p = (char *)KSEG1ADDR(argv[i]); >> + >> + if (argv[i] && *p) { >> + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); >> + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); >> + } >> + } > Why do you need to use kseg1? Why can't the arguments be accessed > cached? > > Are the arguments passed as virtual or physical addresses? If virtual & > we can access them cached then you could replace all of this with a call > to fw_init_cmdline(). this patch only support build-in dts, will remove . >> +static int __init plat_enable_iocoherency(void) >> +{ >> + if (!mips_cps_numiocu(0)) >> + return 0; >> + >> + /* Nothing special needs to be done to enable coherency */ >> + pr_info("Coherence Manager IOCU detected\n"); >> + /* Second IOCU for MPE or other master access register */ >> + write_gcr_reg0_base(0xa0000000); >> + write_gcr_reg0_mask(0xf8000000 | CM_GCR_REGn_MASK_CMTGT_IOCU1); >> + return 1; >> +} >> + >> +static void __init plat_setup_iocoherency(void) >> +{ >> + if (plat_enable_iocoherency() && >> + coherentio == IO_COHERENCE_DISABLED) { >> + pr_info("Hardware DMA cache coherency disabled\n"); >> + return; >> + } >> + panic("This kind of IO coherency is not supported!"); >> +} > Since you select CONFIG_DMA_NONCOHERENT in Kconfig, coherentio will > always equal IO_COHERENCE_DISABLED. That suggests to me that the above 2 > functions are probably useless, or at least needlessly convoluted. Thanks, will remove. >> +static int __init plat_publish_devices(void) >> +{ >> + if (!of_have_populated_dt()) >> + return 0; >> + return of_platform_populate(NULL, of_default_bus_match_table, NULL, >> + NULL); >> +} >> +arch_initcall(plat_publish_devices); > The core DT code calls of_platform_populate() already (see > of_platform_default_populate_init()), so you can remove this function. > > Thanks, > Paul Thanks, will remove. -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index ac7ad54f984f..bcd647060f3e 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -12,6 +12,7 @@ platforms += cobalt platforms += dec platforms += emma platforms += generic +platforms += intel-mips platforms += jazz platforms += jz4740 platforms += lantiq diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 08c10c518f83..2d34f17f3e24 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -409,6 +409,34 @@ config LANTIQ select ARCH_HAS_RESET_CONTROLLER select RESET_CONTROLLER +config INTEL_MIPS + bool "Intel MIPS interAptiv SoC based platforms" + select BOOT_RAW + select CEVT_R4K + select COMMON_CLK + select CPU_MIPS32_3_5_EVA + select CPU_MIPS32_3_5_FEATURES + select CPU_MIPSR2_IRQ_EI + select CPU_MIPSR2_IRQ_VI + select CSRC_R4K + select DMA_NONCOHERENT + select GENERIC_ISA_DMA + select IRQ_MIPS_CPU + select MFD_CORE + select MFD_SYSCON + select MIPS_CPU_SCACHE + select MIPS_GIC + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS32_R3_5 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_MIPS_CPS + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_ZBOOT + select TIMER_OF + select USE_OF + config LASAT bool "LASAT Networks platforms" select CEVT_R4K @@ -1016,6 +1044,7 @@ source "arch/mips/bcm47xx/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/bmips/Kconfig" source "arch/mips/generic/Kconfig" +source "arch/mips/intel-mips/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" source "arch/mips/lantiq/Kconfig" diff --git a/arch/mips/configs/grx500_defconfig b/arch/mips/configs/grx500_defconfig new file mode 100644 index 000000000000..9dd7ba8e1f74 --- /dev/null +++ b/arch/mips/configs/grx500_defconfig @@ -0,0 +1,138 @@ +CONFIG_INTEL_MIPS=y +CONFIG_DTB_INTEL_MIPS_GRX500=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_SCHED_SMT=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_MIPS_CPS=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_NR_CPUS=2 +CONFIG_HZ_100=y +# CONFIG_SECCOMP is not set +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="GRX500" +CONFIG_SYSVIPC=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_INITRAMFS_COMPRESSION_XZ=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_FHANDLE is not set +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEBUG_FS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_ATM=m +CONFIG_ATM_BR2684=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_CONSOLE_TRANSLATIONS is not set +# CONFIG_VT_CONSOLE is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVMEM is not set +CONFIG_SERIAL_LANTIQ=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_VIRTIO_MENU is not set +# CONFIG_MIPS_PLATFORM_DEVICES is not set +CONFIG_INTEL_CGU_CLK=y +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_MANDATORY_FILE_LOCKING is not set +CONFIG_QUOTA=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_PROC_KCORE=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_TMPFS_XATTR=y +CONFIG_CONFIGFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NLS=y +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DEBUG_INFO=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_FRAME_WARN=2048 +CONFIG_STRIP_ASM_SYMS=y +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +CONFIG_HEADERS_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_LIBCRC32C=y +CONFIG_IRQ_POLL=y diff --git a/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h b/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h new file mode 100644 index 000000000000..ac5f3b943d2a --- /dev/null +++ b/arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * Copyright (C) 2018 Intel Corporation. + */ + +#ifndef __ASM_MACH_INTEL_MIPS_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_INTEL_MIPS_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_mmips 0 +#define cpu_has_vz 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_dsp2 0 +#define cpu_has_mipsmt 1 + +#define cpu_has_vint 1 +#define cpu_has_veic 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_has_cm2 1 +#define cpu_has_cm2_l2sync 1 +#define cpu_has_eva 1 +#define cpu_has_tlbinv 1 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + +#endif /* __ASM_MACH_INTEL_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-intel-mips/ioremap.h b/arch/mips/include/asm/mach-intel-mips/ioremap.h new file mode 100644 index 000000000000..99b20ed0b457 --- /dev/null +++ b/arch/mips/include/asm/mach-intel-mips/ioremap.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Lei Chuanhua <Chuanhua.lei@lantiq.com> + * Copyright (C) 2018 Intel Corporation. + */ +#ifndef __ASM_MACH_INTEL_MIPS_IOREMAP_H +#define __ASM_MACH_INTEL_MIPS_IOREMAP_H + +#include <linux/types.h> + +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +/* + * TOP IO Space definition for SSX7 components /PCIe/ToE/Memcpy + * physical 0xa0000000 --> virtual 0xe0000000 + */ +#define GRX500_TOP_IOREMAP_BASE 0xA0000000 +#define GRX500_TOP_IOREMAP_SIZE 0x20000000 +#define GRX500_TOP_IOREMAP_PHYS_VIRT_OFFSET 0x40000000 + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (offset >= GRX500_TOP_IOREMAP_BASE && + offset < (GRX500_TOP_IOREMAP_BASE + GRX500_TOP_IOREMAP_SIZE)) + return (void __iomem *)(unsigned long) + (offset + GRX500_TOP_IOREMAP_PHYS_VIRT_OFFSET); + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return (unsigned long)addr >= (unsigned long)GRX500_TOP_IOREMAP_BASE; +} +#endif /* __ASM_MACH_INTEL_MIPS_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-intel-mips/irq.h b/arch/mips/include/asm/mach-intel-mips/irq.h new file mode 100644 index 000000000000..12a949084856 --- /dev/null +++ b/arch/mips/include/asm/mach-intel-mips/irq.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Lei Chuanhua <Chuanhua.lei@lantiq.com> + * Copyright (C) 2018 Intel Corporation. + */ + +#ifndef __INTEL_MIPS_IRQ_H +#define __INTEL_MIPS_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) + +#define NR_IRQS 256 + +#include_next <irq.h> + +#endif /* __INTEL_MIPS_IRQ_H */ diff --git a/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h b/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h new file mode 100644 index 000000000000..a30542eca9ec --- /dev/null +++ b/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Chris Dearman (chris@mips.com) + * Leonid Yegoshin (yegoshin@mips.com) + * Copyright (C) 2012 Mips Technologies, Inc. + * Copyright (C) 2018 Intel Corporation. + */ +#ifndef __ASM_MACH_INTEL_MIPS_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_INTEL_MIPS_KERNEL_ENTRY_INIT_H +/* +* Prepare segments for EVA boot: +* +* This is in case the processor boots in legacy configuration +* (SI_EVAReset is de-asserted and CONFIG5.K == 0) with 1GB DDR +* +* On entry, t1 is loaded with CP0_CONFIG +* +* ========================= Mappings ============================= +* Virtual memory Physical memory Mapping +* 0x00000000 - 0x7fffffff 0x20000000 - 0x9ffffffff MUSUK (kuseg) +* 0x80000000 - 0x9fffffff 0x80000000 - 0x9ffffffff UK (kseg0) +* 0xa0000000 - 0xbfffffff 0x20000000 - 0x3ffffffff UK (kseg1) +* 0xc0000000 - 0xdfffffff - MSK (kseg2) +* 0xe0000000 - 0xffffffff 0xa0000000 - 0xbfffffff UK 2nd IO +* +* user space virtual: 0x00000000 ~ 0x7fffffff +* kernel space virtual: 0x60000000 ~ 0x9fffffff +* physical: 0x20000000 ~ 0x5fffffff (flat 1GB) +* user/kernel space overlapped from 0x60000000 ~ 0x7fffffff (virtual) +* where physical 0x20000000 ~ 0x2fffffff (cached and uncached) +* virtual 0xa0000000 ~ 0xafffffff (1st IO space) +* virtual 0xf0000000 ~ 0xffffffff (2nd IO space) +* +* The last 64KB of physical memory are reserved for correct HIGHMEM +* macros arithmetics. +* Detailed KSEG and PHYS_OFFSET and PAGE_OFFSEt adaption, refer to +* asm/mach-intel-mips/spaces.h +*/ + .macro platform_eva_init + + .set push + .set reorder + /* + * Get Config.K0 value and use it to program + * the segmentation registers + */ + mfc0 t1, CP0_CONFIG + andi t1, 0x7 /* CCA */ + move t2, t1 + ins t2, t1, 16, 3 + /* SegCtl0 */ + li t0, ((MIPS_SEGCFG_UK << MIPS_SEGCFG_AM_SHIFT) | \ + (5 << MIPS_SEGCFG_PA_SHIFT) | (2 << MIPS_SEGCFG_C_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) | \ + (((MIPS_SEGCFG_MSK << MIPS_SEGCFG_AM_SHIFT) | \ + (0 << MIPS_SEGCFG_PA_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) + ins t0, t1, 16, 3 + mtc0 t0, $5, 2 + + /* SegCtl1 */ + li t0, ((MIPS_SEGCFG_UK << MIPS_SEGCFG_AM_SHIFT) | \ + (1 << MIPS_SEGCFG_PA_SHIFT) | (2 << MIPS_SEGCFG_C_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) | \ + (((MIPS_SEGCFG_UK << MIPS_SEGCFG_AM_SHIFT) | \ + (2 << MIPS_SEGCFG_PA_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) + ins t0, t1, 16, 3 + mtc0 t0, $5, 3 + + /* SegCtl2 */ + li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ + (0 << MIPS_SEGCFG_PA_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) | \ + (((MIPS_SEGCFG_MUSK << MIPS_SEGCFG_AM_SHIFT) | \ + (0 << MIPS_SEGCFG_PA_SHIFT)/*| (2 << MIPS_SEGCFG_C_SHIFT)*/ | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) + ins t0, t1, 0, 3 + mtc0 t0, $5, 4 + + jal mips_ihb + mfc0 t0, $16, 5 + li t2, 0x40000000 /* K bit */ + or t0, t0, t2 + mtc0 t0, $16, 5 + sync + jal mips_ihb + + .set pop + .endm + + .macro kernel_entry_setup + sync + ehb + platform_eva_init + .endm + + .macro smp_slave_setup + sync + ehb + platform_eva_init + .endm + +#endif /* __ASM_MACH_INTEL_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/arch/mips/include/asm/mach-intel-mips/spaces.h b/arch/mips/include/asm/mach-intel-mips/spaces.h new file mode 100644 index 000000000000..80e7b09f712c --- /dev/null +++ b/arch/mips/include/asm/mach-intel-mips/spaces.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Author: Leonid Yegoshin (yegoshin@mips.com) + * Copyright (C) 2012 MIPS Technologies, Inc. + * Copyright (C) 2014 Lei Chuanhua <Chuanhua.lei@lantiq.com> + * Copyright (C) 2018 Intel Corporation. + */ + +#ifndef _ASM_INTEL_MIPS_SPACES_H +#define _ASM_INTEL_MIPS_SPACES_H + +#define PAGE_OFFSET _AC(0x60000000, UL) +#define PHYS_OFFSET _AC(0x20000000, UL) + +/* No Highmem Support */ +#define HIGHMEM_START _AC(0xffff0000, UL) + +#define FIXADDR_TOP ((unsigned long)(long)(int)0xcffe0000) + +#define IO_SIZE _AC(0x10000000, UL) +#define IO_SHIFT _AC(0x10000000, UL) + +/* IO space one */ +#define __pa_symbol(x) __pa(x) + +#include <asm/mach-generic/spaces.h> +#endif /* __ASM_INTEL_MIPS_SPACES_H */ diff --git a/arch/mips/include/asm/mach-intel-mips/war.h b/arch/mips/include/asm/mach-intel-mips/war.h new file mode 100644 index 000000000000..1c95553151e1 --- /dev/null +++ b/arch/mips/include/asm/mach-intel-mips/war.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MIPS_MACH_INTEL_MIPS_WAR_H +#define __ASM_MIPS_MACH_INTEL_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_INTEL_MIPS_WAR_H */ diff --git a/arch/mips/intel-mips/Kconfig b/arch/mips/intel-mips/Kconfig new file mode 100644 index 000000000000..35d2ae2b5408 --- /dev/null +++ b/arch/mips/intel-mips/Kconfig @@ -0,0 +1,22 @@ +if INTEL_MIPS + +choice + prompt "Built-in device tree" + help + Legacy bootloaders do not pass a DTB pointer to the kernel, so + if a "wrapper" is not being used, the kernel will need to include + a device tree that matches the target board. + + The builtin DTB will only be used if the firmware does not supply + a valid DTB. + +config DTB_INTEL_MIPS_NONE + bool "None" + +config DTB_INTEL_MIPS_GRX500 + bool "Intel MIPS GRX500 Board" + select BUILTIN_DTB + +endchoice + +endif diff --git a/arch/mips/intel-mips/Makefile b/arch/mips/intel-mips/Makefile new file mode 100644 index 000000000000..9067d0dd20a0 --- /dev/null +++ b/arch/mips/intel-mips/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += prom.o +obj-y += irq.o +obj-y += time.o diff --git a/arch/mips/intel-mips/Platform b/arch/mips/intel-mips/Platform new file mode 100644 index 000000000000..3976788698e3 --- /dev/null +++ b/arch/mips/intel-mips/Platform @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# MIPS SoC platform +# + +platform-$(CONFIG_INTEL_MIPS) += intel-mips/ +cflags-$(CONFIG_INTEL_MIPS) += -I$(srctree)/arch/mips/include/asm/mach-intel-mips +ifdef CONFIG_EVA + load-$(CONFIG_INTEL_MIPS) = 0xffffffff60020000 +else + load-$(CONFIG_INTEL_MIPS) = 0xffffffff80020000 +endif diff --git a/arch/mips/intel-mips/irq.c b/arch/mips/intel-mips/irq.c new file mode 100644 index 000000000000..b126c98fb391 --- /dev/null +++ b/arch/mips/intel-mips/irq.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Intel Corporation. + */ +#include <linux/init.h> +#include <linux/irqchip.h> +#include <linux/of_irq.h> +#include <asm/irq.h> +#include <asm/irq_cpu.h> + +void __init arch_init_irq(void) +{ + struct device_node *intc_node; + + pr_info("EIC is %s\n", cpu_has_veic ? "on" : "off"); + pr_info("VINT is %s\n", cpu_has_vint ? "on" : "off"); + + intc_node = of_find_compatible_node(NULL, NULL, + "mti,cpu-interrupt-controller"); + if (!cpu_has_veic && !intc_node) + mips_cpu_irq_init(); + + irqchip_init(); +} + +int get_c0_perfcount_int(void) +{ + return gic_get_c0_perfcount_int(); +} +EXPORT_SYMBOL_GPL(get_c0_perfcount_int); + +unsigned int get_c0_compare_int(void) +{ + return gic_get_c0_compare_int(); +} diff --git a/arch/mips/intel-mips/prom.c b/arch/mips/intel-mips/prom.c new file mode 100644 index 000000000000..a1b1393c13bc --- /dev/null +++ b/arch/mips/intel-mips/prom.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014 Lei Chuanhua <Chuanhua.lei@lantiq.com> + * Copyright (C) 2016 Intel Corporation. + */ +#include <linux/export.h> +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/of_fdt.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> +#include <asm/dma-coherence.h> +#include <asm/mips-cps.h> +#include <asm/prom.h> +#include <asm/smp-ops.h> + +#define CPC_BASE_ADDR 0x12310000 +#define IOPORT_RESOURCE_START 0x10000000 +#define IOMEM_RESOURCE_START 0x10000000 + +const char *get_system_type(void) +{ + return "Intel MIPS interAptiv SoC"; +} + +void prom_free_prom_memory(void) +{ +} + +static void __init prom_init_cmdline(void) +{ + int i; + int argc; + char **argv; + + /* + * If u-boot pass parameters, it is ok, however, if without u-boot + * JTAG or other tool has to reset all register value before it goes + * emulation most likely belongs to this category + */ + if (fw_arg0 == 0 || fw_arg1 == 0) + return; + + /* + * a0: fw_arg0 - the number of string in init cmdline + * a1: fw_arg1 - the address of string in init cmdline + * + * In accordance with the MIPS UHI specification, + * the bootloader can pass the following arguments to the kernel: + * - $a0: -2. + * - $a1: KSEG0 address of the flattened device-tree blob. + */ + if (fw_arg0 == -2) + return; + + argc = fw_arg0; + argv = (char **)KSEG1ADDR(fw_arg1); + + arcs_cmdline[0] = '\0'; + + for (i = 0; i < argc; i++) { + char *p = (char *)KSEG1ADDR(argv[i]); + + if (argv[i] && *p) { + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + } + } +} + +static int __init plat_enable_iocoherency(void) +{ + if (!mips_cps_numiocu(0)) + return 0; + + /* Nothing special needs to be done to enable coherency */ + pr_info("Coherence Manager IOCU detected\n"); + /* Second IOCU for MPE or other master access register */ + write_gcr_reg0_base(0xa0000000); + write_gcr_reg0_mask(0xf8000000 | CM_GCR_REGn_MASK_CMTGT_IOCU1); + return 1; +} + +static void __init plat_setup_iocoherency(void) +{ + if (plat_enable_iocoherency() && + coherentio == IO_COHERENCE_DISABLED) { + pr_info("Hardware DMA cache coherency disabled\n"); + return; + } + panic("This kind of IO coherency is not supported!"); +} + +static void free_init_pages_eva_intel(void *begin, void *end) +{ + free_init_pages("unused kernel", __pa_symbol((unsigned long *)begin), + __pa_symbol((unsigned long *)end)); +} + +static void plat_early_init_devtree(void) +{ + void *dtb = NULL; + + /* + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + if (fw_passed_dtb) /* used by CONFIG_MIPS_APPENDED_RAW_DTB as well */ + dtb = (void *)fw_passed_dtb; + else if (__dtb_start != __dtb_end) + dtb = (void *)__dtb_start; + else + panic("no dtb found"); + + if (dtb) + __dt_setup_arch(dtb); +} + +void __init plat_mem_setup(void) +{ + ioport_resource.start = IOPORT_RESOURCE_START; + ioport_resource.end = ~0UL; /* No limit */ + iomem_resource.start = IOMEM_RESOURCE_START; + iomem_resource.end = ~0UL; /* No limit */ + + set_io_port_base((unsigned long)KSEG1); + + strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); + + plat_early_init_devtree(); + plat_setup_iocoherency(); + + if (IS_ENABLED(CONFIG_EVA)) + free_init_pages_eva = free_init_pages_eva_intel; + else + free_init_pages_eva = 0; +} + +void __init device_tree_init(void) +{ + unflatten_and_copy_device_tree(); +} + +phys_addr_t mips_cpc_default_phys_base(void) +{ + return CPC_BASE_ADDR; +} + +void __init prom_init(void) +{ + prom_init_cmdline(); + + mips_cpc_probe(); + + if (!register_cps_smp_ops()) + return; + + if (!register_cmp_smp_ops()) + return; + + if (!register_vsmp_smp_ops()) + return; +} + +static int __init plat_publish_devices(void) +{ + if (!of_have_populated_dt()) + return 0; + return of_platform_populate(NULL, of_default_bus_match_table, NULL, + NULL); +} +arch_initcall(plat_publish_devices); diff --git a/arch/mips/intel-mips/time.c b/arch/mips/intel-mips/time.c new file mode 100644 index 000000000000..deb462c21df6 --- /dev/null +++ b/arch/mips/intel-mips/time.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Intel Corporation. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/of.h> + +#include <asm/time.h> + +void __init plat_time_init(void) +{ + unsigned long cpuclk; + struct device_node *np; + struct clk *clk; + + of_clk_init(NULL); + + np = of_get_cpu_node(0, NULL); + if (!np) { + pr_err("Failed to get CPU node\n"); + return; + } + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); + return; + } + + cpuclk = clk_get_rate(clk); + /* the chip resolution is the half of the clock*/ + mips_hpt_frequency = cpuclk / 2; + clk_put(clk); + + write_c0_compare(read_c0_count()); + pr_info("CPU Clock: %ldHz mips_hpt_frequency %dHz\n", + cpuclk, mips_hpt_frequency); + timer_probe(); +}