| Message ID | 20180808171952.17263-1-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: sunxi-ng: fix H6 bus clocks divider position | expand |
On Thu, Aug 9, 2018 at 1:19 AM, Icenowy Zheng <icenowy@aosc.io> wrote: > The bus clocks (AHB/APB) on Allwinner H6 have their second divider start > at bit 8, according to the user manual and the BSP code. However, > currently the divider is wrongly set to 16, thus the divider is not > correctly read and the clock frequency is not correctly calculated. > > Fix this bit offset on all affected bus clocks in ccu-sun50i-h6. > > Cc: stable@vger.kernel.org # v4.17.y > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> APB1 seems to be the only affected bus. Since there aren't any users ATM, I've queued this up for 4.20, with a few minor tweaks to the commit log: - s/wrongly/incorrectly/ - subject changed to "clk: sunxi-ng: h6: fix bus clocks' divider position" - third line: currently the divider _offset_ is ... ChenYu
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index bdbfe78fe133..0f7a0ffd3f70 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -224,7 +224,7 @@ static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2", psi_ahb1_ahb2_parents, 0x510, 0, 5, /* M */ - 16, 2, /* P */ + 8, 2, /* P */ 24, 2, /* mux */ 0); @@ -233,19 +233,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k", "pll-periph0" }; static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c, 0, 5, /* M */ - 16, 2, /* P */ + 8, 2, /* P */ 24, 2, /* mux */ 0); static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520, 0, 5, /* M */ - 16, 2, /* P */ + 8, 2, /* P */ 24, 2, /* mux */ 0); static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524, 0, 5, /* M */ - 16, 2, /* P */ + 8, 2, /* P */ 24, 2, /* mux */ 0);
The bus clocks (AHB/APB) on Allwinner H6 have their second divider start at bit 8, according to the user manual and the BSP code. However, currently the divider is wrongly set to 16, thus the divider is not correctly read and the clock frequency is not correctly calculated. Fix this bit offset on all affected bus clocks in ccu-sun50i-h6. Cc: stable@vger.kernel.org # v4.17.y Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)