| Message ID | 20180926133956.79788-1-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: renesas: r7s9210: Add SPI clocks | expand |
On Wed, Sep 26, 2018 at 3:40 PM Chris Brandt <chris.brandt@renesas.com> wrote: > Add RSPI clocks for RZ/A2. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in clk-renesas-for-v4.20. Gr{oetje,eeting}s, Geert
On Wed, Sep 26, 2018 at 08:39:56AM -0500, Chris Brandt wrote: > Add RSPI clocks for RZ/A2. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index d8ff4cb0defc..5135f13ec628 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -95,6 +95,9 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1), DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1), + DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1), + DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1), + DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1), }; /* The clock dividers in the table vary based on DT and register settings */
Add RSPI clocks for RZ/A2. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- drivers/clk/renesas/r7s9210-cpg-mssr.c | 3 +++ 1 file changed, 3 insertions(+)