| Message ID | 20181018070729.52943-1-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [v2] clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock | expand |
On Thu, Oct 18, 2018 at 03:07:29PM +0800, Icenowy Zheng wrote: > In the user manual of A64 SoC, the bit 22 and 23 of pll-mipi control > register is called "LDO{1,2}_EN", and according to the BSP source code > from Allwinner , the LDOs are enabled during the clock's enabling > process. > > The clock failed to generate output if the two LDOs are not enabled. > > Add the two bits to the clock's gate bits, so that the LDOs are enabled > when the PLL is enabled. > > Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Queued for 4.21, thanks! Maxime
Quoting Icenowy Zheng (2018-10-18 00:07:29) > In the user manual of A64 SoC, the bit 22 and 23 of pll-mipi control > register is called "LDO{1,2}_EN", and according to the BSP source code > from Allwinner , the LDOs are enabled during the clock's enabling > process. > > The clock failed to generate output if the two LDOs are not enabled. > > Add the two bits to the clock's gate bits, so that the LDOs are enabled > when the PLL is enabled. > > Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- Looks OK to me from not knowing anything about this driver. Shall I pick directly into clk-next for next release?
于 2018年10月19日 GMT+08:00 上午1:19:54, Stephen Boyd <sboyd@kernel.org> 写到: >Quoting Icenowy Zheng (2018-10-18 00:07:29) >> In the user manual of A64 SoC, the bit 22 and 23 of pll-mipi control >> register is called "LDO{1,2}_EN", and according to the BSP source >code >> from Allwinner , the LDOs are enabled during the clock's enabling >> process. >> >> The clock failed to generate output if the two LDOs are not enabled. >> >> Add the two bits to the clock's gate bits, so that the LDOs are >enabled >> when the PLL is enabled. >> >> Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- > >Looks OK to me from not knowing anything about this driver. Shall I >pick >directly into clk-next for next release? I prefer to wait for an ACK from Maxime. > > >_______________________________________________ >linux-arm-kernel mailing list >linux-arm-kernel@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 5f80eb018014..884d8f7863c4 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -162,7 +162,12 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", #define SUN50I_A64_PLL_MIPI_REG 0x040 static struct ccu_nkm pll_mipi_clk = { - .enable = BIT(31), + /* + * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's + * user manual, and by experiments the PLL doesn't work without + * these bits toggled. + */ + .enable = BIT(31) | BIT(23) | BIT(22), .lock = BIT(28), .n = _SUNXI_CCU_MULT(8, 4), .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
In the user manual of A64 SoC, the bit 22 and 23 of pll-mipi control register is called "LDO{1,2}_EN", and according to the BSP source code from Allwinner , the LDOs are enabled during the clock's enabling process. The clock failed to generate output if the two LDOs are not enabled. Add the two bits to the clock's gate bits, so that the LDOs are enabled when the PLL is enabled. Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Changes in v2: - Add a section of comments before the addition. drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)