clk: ingenic: jz4740: Fix gating of UDC clock

Commit Message

Paul Cercueil Jan. 25, 2019, 3:34 p.m. UTC

The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <[e-mail]>
Tested-by: Artur Rojek <[e-mail]>
---
 drivers/clk/ingenic/jz4740-cgu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Stephen Boyd Jan. 25, 2019, 6:55 p.m. UTC | #1

Quoting Paul Cercueil (2019-01-25 07:34:36)
> The UDC clock is gated when the bit is cleared, not when it is set.
> 
> Signed-off-by: Paul Cercueil <[e-mail]>
> Tested-by: Artur Rojek <[e-mail]>
> ---

Any Fixes tag for this?

Paul Cercueil Jan. 25, 2019, 7:24 p.m. UTC | #2

Hi,


On Fri, Jan 25, 2019 at 3:55 PM, Stephen Boyd <[e-mail]> wrote:
> Quoting Paul Cercueil (2019-01-25 07:34:36)
>>  The UDC clock is gated when the bit is cleared, not when it is set.
>> 
>>  Signed-off-by: Paul Cercueil <[e-mail] 
>> <mailto:[e-mail]>>
>>  Tested-by: Artur Rojek <[e-mail] 
>> <mailto:[e-mail]>>
>>  ---
> 
> Any Fixes tag for this?
> 

Fixes: 2b555a4b9cae

Should I resend?

Stephen Boyd Jan. 29, 2019, 6:13 p.m. UTC | #3

Quoting Paul Cercueil (2019-01-25 11:24:58)
> Hi,
> 
> 
> On Fri, Jan 25, 2019 at 3:55 PM, Stephen Boyd <[e-mail]> wrote:
> > Quoting Paul Cercueil (2019-01-25 07:34:36)
> >>  The UDC clock is gated when the bit is cleared, not when it is set.
> >> 
> >>  Signed-off-by: Paul Cercueil <[e-mail] 
> >> <mailto:[e-mail]>>
> >>  Tested-by: Artur Rojek <[e-mail] 
> >> <mailto:[e-mail]>>
> >>  ---
> > 
> > Any Fixes tag for this?
> > 
> 
> Fixes: 2b555a4b9cae
> 
> Should I resend?
> 

No need to resend. Is this fixing something that's broken in the v5.0-rc
series? I'm trying to understand if this is a critical fix or a
non-critical fix that can bake until the next release cycle.

Paul Cercueil Jan. 29, 2019, 7:22 p.m. UTC | #4

Hi,

Le mar. 29 janv. 2019 à 15:13, Stephen Boyd <[e-mail]> a 
écrit :
> Quoting Paul Cercueil (2019-01-25 11:24:58)
>>  Hi,
>> 
>> 
>>  On Fri, Jan 25, 2019 at 3:55 PM, Stephen Boyd <[e-mail]> 
>> wrote:
>>  > Quoting Paul Cercueil (2019-01-25 07:34:36)
>>  >>  The UDC clock is gated when the bit is cleared, not when it is 
>> set.
>>  >>
>>  >>  Signed-off-by: Paul Cercueil <[e-mail]
>>  >> <mailto:[e-mail]>>
>>  >>  Tested-by: Artur Rojek <[e-mail]
>>  >> <mailto:[e-mail]>>
>>  >>  ---
>>  >
>>  > Any Fixes tag for this?
>>  >
>> 
>>  Fixes: 2b555a4b9cae
>> 
>>  Should I resend?
>> 
> 
> No need to resend. Is this fixing something that's broken in the 
> v5.0-rc
> series? I'm trying to understand if this is a critical fix or a
> non-critical fix that can bake until the next release cycle.

It's been broken for one year and nobody noticed, it can wait for 5.1.

-Paul

Stephen Boyd Jan. 29, 2019, 9:16 p.m. UTC | #5

Quoting Paul Cercueil (2019-01-29 11:22:25)
> Hi,
> 
> Le mar. 29 janv. 2019 à 15:13, Stephen Boyd <[e-mail]> a 
> écrit :
> > Quoting Paul Cercueil (2019-01-25 11:24:58)
> >>  Hi,
> >> 
> >> 
> >>  On Fri, Jan 25, 2019 at 3:55 PM, Stephen Boyd <[e-mail]> 
> >> wrote:
> >>  > Quoting Paul Cercueil (2019-01-25 07:34:36)
> >>  >>  The UDC clock is gated when the bit is cleared, not when it is 
> >> set.
> >>  >>
> >>  >>  Signed-off-by: Paul Cercueil <[e-mail]
> >>  >> <mailto:[e-mail]>>
> >>  >>  Tested-by: Artur Rojek <[e-mail]
> >>  >> <mailto:[e-mail]>>
> >>  >>  ---
> >>  >
> >>  > Any Fixes tag for this?
> >>  >
> >> 
> >>  Fixes: 2b555a4b9cae
> >> 
> >>  Should I resend?
> >> 
> > 
> > No need to resend. Is this fixing something that's broken in the 
> > v5.0-rc
> > series? I'm trying to understand if this is a critical fix or a
> > non-critical fix that can bake until the next release cycle.
> 
> It's been broken for one year and nobody noticed, it can wait for 5.1.
> 

Ok, thanks!

Stephen Boyd Feb. 5, 2019, 9:32 p.m. UTC | #6

Quoting Paul Cercueil (2019-01-25 07:34:36)
> The UDC clock is gated when the bit is cleared, not when it is set.
> 
> Signed-off-by: Paul Cercueil <[e-mail]>
> Tested-by: Artur Rojek <[e-mail]>
> ---

Applied to clk-next

Patch

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index d8ac7f2e183a..5d0d5be1e6a7 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -165,7 +165,7 @@  static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
 		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
 		.mux = { CGU_REG_CPCCR, 29, 1 },
 		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
-		.gate = { CGU_REG_SCR, 6 },
+		.gate = { CGU_REG_SCR, 6, true },
 	},
 
 	/* Gate-only clocks */