diff mbox series

clk: imx8mq: Add missing M4 clocks

Message ID 20190130201725.18961-1-ccaione@baylibre.com (mailing list archive)
State Accepted, archived
Headers show
Series clk: imx8mq: Add missing M4 clocks | expand

Commit Message

Carlo Caione Jan. 30, 2019, 8:17 p.m. UTC 
The clocks list is missing the clocks for the the M4 core.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
 drivers/clk/imx/clk-imx8mq.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Fabio Estevam Jan. 30, 2019, 10:46 p.m. UTC | #1 
On Wed, Jan 30, 2019 at 6:17 PM Carlo Caione <ccaione@baylibre.com> wrote:
>
> The clocks list is missing the clocks for the the M4 core.

There is a repeated "the" in this phrase.

> Signed-off-by: Carlo Caione <ccaione@baylibre.com>

Reviewed-by: Fabio Esteva, <festevam@gmail.com>
Fabio Estevam Jan. 30, 2019, 11:55 p.m. UTC | #2 
On Wed, Jan 30, 2019 at 8:46 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> On Wed, Jan 30, 2019 at 6:17 PM Carlo Caione <ccaione@baylibre.com> wrote:
> >
> > The clocks list is missing the clocks for the the M4 core.
>
> There is a repeated "the" in this phrase.
>
> > Signed-off-by: Carlo Caione <ccaione@baylibre.com>
>
> Reviewed-by: Fabio Esteva, <festevam@gmail.com>

I meant this instead ;-) :

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Carlo Caione Jan. 31, 2019, 9:09 a.m. UTC | #3 
On 30/01/2019 22:46, Fabio Estevam wrote:
> On Wed, Jan 30, 2019 at 6:17 PM Carlo Caione <ccaione@baylibre.com> wrote:
>>
>> The clocks list is missing the clocks for the the M4 core.
> 
> There is a repeated "the" in this phrase.

Ouch! Can I count on the maintainer to fix this while merging? ;)

Thanks,

--
Carlo Caione
Stephen Boyd Feb. 5, 2019, 10:33 p.m. UTC | #4 
Quoting Carlo Caione (2019-01-31 01:09:52)
> On 30/01/2019 22:46, Fabio Estevam wrote:
> > On Wed, Jan 30, 2019 at 6:17 PM Carlo Caione <ccaione@baylibre.com> wrote:
> >>
> >> The clocks list is missing the clocks for the the M4 core.
> > 
> > There is a repeated "the" in this phrase.
> 
> Ouch! Can I count on the maintainer to fix this while merging? ;)
> 

If I remember....
Stephen Boyd Feb. 21, 2019, 8:45 p.m. UTC | #5 
Quoting Carlo Caione (2019-01-30 12:17:25)
> The clocks list is missing the clocks for the the M4 core.
> 
> Signed-off-by: Carlo Caione <ccaione@baylibre.com>
> ---

Applied to clk-next plus all the fixes
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 398ab0bcd9de..c02c43fcb892 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -48,6 +48,9 @@  static const char * const dram_pll2_out_sels[] = {"dram_pll2_div", "dram_pll1_re
 static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
 					"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
 
+static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
+					"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
+
 static const char * const imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
 					"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
 
@@ -396,15 +399,19 @@  static int imx8mq_clocks_probe(struct platform_device *pdev)
 
 	/* CORE */
 	clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
+	clks[IMX8MQ_CLK_M4_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mq_arm_m4_sels, ARRAY_SIZE(imx8mq_arm_m4_sels));
 	clks[IMX8MQ_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));
 	clks[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3,  imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));
 	clks[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels,  ARRAY_SIZE(imx8mq_gpu_shader_sels));
+
 	clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
+	clks[IMX8MQ_CLK_M4_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
 	clks[IMX8MQ_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28);
 	clks[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
 	clks[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
 
 	clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+	clks[IMX8MQ_CLK_M4_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
 	clks[IMX8MQ_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
 	clks[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
 	clks[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);