| Message ID | 20190312152256.35574-13-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Support for Allwinner V3/S3L and Sochip S3 | expand |
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 21e1806ca509..10795b5ec376 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -304,6 +304,11 @@ function = "uart0"; }; + uart2_pins: uart2-pins { + pins = "PB0", "PB1"; + function = "uart2"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -377,6 +382,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; status = "disabled"; };
The UART2 RX/TX pins on Allwinner V3 series is at PB0/1, which is used as debugging UART on some boards. Add pinctrl node for them. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)