Message ID | 20190411214835.19947-2-digetx@gmail.com (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | clk: Tegra124 PLLM fixes | expand |
Quoting Dmitry Osipenko (2019-04-11 14:48:34) > There are wrongly set parenthesis in the code that are resulting in a > wrong configuration being programmed for PLLM. The original fix was made > by Danny Huang in the downstream kernel. The patch was tested on Nyan Big > Tegra124 chromebook, PLLM rate changing works correctly now and system > doesn't lock up after changing the PLLM rate due to EMC scaling. > > Cc: <stable@vger.kernel.org> > Tested-by: Steev Klimaszewski <steev@kali.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- Applied to clk-next
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index b50b7460014b..3e67cbcd80da 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -663,8 +663,8 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll, pll_override_writel(val, params->pmc_divp_reg, pll); val = pll_override_readl(params->pmc_divnm_reg, pll); - val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | - ~(divn_mask(pll) << div_nmp->override_divn_shift); + val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | + (divn_mask(pll) << div_nmp->override_divn_shift)); val |= (cfg->m << div_nmp->override_divm_shift) | (cfg->n << div_nmp->override_divn_shift); pll_override_writel(val, params->pmc_divnm_reg, pll);