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[46.91.239.54]) by smtp.gmail.com with ESMTPSA id d3sm179133wrs.8.2019.06.13.09.12.27 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 13 Jun 2019 09:12:27 -0700 (PDT) From: Thierry Reding To: Michael Turquette , Stephen Boyd Cc: Jonathan Hunter , Peter De Schrijver , Alex Frid , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 2/3] clk: tegra: Warn if an enabled PLL is in IDDQ Date: Thu, 13 Jun 2019 18:12:24 +0200 Message-Id: <20190613161225.2531-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190613161225.2531-1-thierry.reding@gmail.com> References: <20190613161225.2531-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a configuration that makes sense, so warn about it. Signed-off-by: Thierry Reding Acked-by: Jon Hunter --- drivers/clk/tegra/clk-tegra210.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 4904ac4a75db..793c7acaf4e2 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -1003,8 +1003,12 @@ static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) _pll_misc_chk_default(clk_base, pllre->params, 0, val, ~mask & PLLRE_MISC0_WRITE_MASK); - /* Enable lock detect */ + /* The PLL doesn't work if it's in IDDQ. */ val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); + if (val & PLLRE_MISC0_IDDQ) + pr_warn("unexpected IDDQ bit set for enabled clock\n"); + + /* Enable lock detect */ val &= ~mask; val |= PLLRE_MISC0_DEFAULT_VALUE & mask; writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);