@@ -345,14 +345,14 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
}
static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
+ unsigned long parent_rate)
{
struct sd_clock *clock = to_sd_clock(hw);
- unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
unsigned int i;
for (i = 0; i < clock->div_num; i++)
- if (div == clock->div_table[i].div)
+ if (rate == DIV_ROUND_CLOSEST(parent_rate,
+ clock->div_table[i].div))
break;
if (i >= clock->div_num)
The .set_rate() callback for the SD clocks is always called with a valid clock rate, returned by .round_rate(). Hence there is no need to iterate through the divider table twice: once to repeat the work done by .round_rate(), and a second time to find the corresponding divider entry. Just iterate once, looking for the divider that matches the passed clock rate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- drivers/clk/renesas/rcar-gen3-cpg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)