| Message ID | 20190623043801.14040-9-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Support for Allwinner V3/S3L and Sochip S3 | expand |
Hi, On Sun, Jun 23, 2019 at 12:38:00PM +0800, Icenowy Zheng wrote: > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes in v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml > index 000a00d12d6a..48c126a7a848 100644 > --- a/Documentation/devicetree/bindings/arm/sunxi.yaml > +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml > @@ -353,6 +353,11 @@ properties: > - const: licheepi,licheepi-zero > - const: allwinner,sun8i-v3s > > + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) > + items: > + - const: sipeed,lichee-zero-plus > + - const: allwinner,sun8i-s3 > + I didn't notice this before, but since this is not a LicheePi, it should be before it, not after. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 000a00d12d6a..48c126a7a848 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -353,6 +353,11 @@ properties: - const: licheepi,licheepi-zero - const: allwinner,sun8i-v3s + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) + items: + - const: sipeed,lichee-zero-plus + - const: allwinner,sun8i-s3 + - description: Linksprite PCDuino items: - const: linksprite,a10-pcduino
The Lichee Zero Plus is a core board made by Sipeed, with a microUSB connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. It has a gold finger connector for expansion, and UART is available from reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or Allwinner V3L SoCs. Add the device tree binding of the basic version of the core board -- w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- No changes in v3. Patch introduced in v2. Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+)