From patchwork Mon Aug 5 10:03:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC39D14E5 for ; Mon, 5 Aug 2019 10:03:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C91CC28372 for ; Mon, 5 Aug 2019 10:03:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD78328861; Mon, 5 Aug 2019 10:03:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 43E7A28372 for ; Mon, 5 Aug 2019 10:03:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727830AbfHEKD3 (ORCPT ); Mon, 5 Aug 2019 06:03:29 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:37909 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728244AbfHEKD2 (ORCPT ); Mon, 5 Aug 2019 06:03:28 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 38FD360019; Mon, 5 Aug 2019 10:03:25 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Ben Peled , Miquel Raynal Subject: [PATCH 7/8] clk: mvebu: ap806: Prepare the introduction of AP807 clock support Date: Mon, 5 Aug 2019 12:03:09 +0200 Message-Id: <20190805100310.29048-8-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Peled Factor out the code that is only useful to AP806 so it will be easier to support AP807. No functional changes. Signed-off-by: Ben Peled Signed-off-by: Miquel Raynal --- drivers/clk/mvebu/ap806-system-controller.c | 146 +++++++++++--------- 1 file changed, 80 insertions(+), 66 deletions(-) diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c index bc43adff02e0..c64e2cc4a3ba 100644 --- a/drivers/clk/mvebu/ap806-system-controller.c +++ b/drivers/clk/mvebu/ap806-system-controller.c @@ -30,6 +30,78 @@ static struct clk_onecell_data ap806_clk_data = { .clk_num = AP806_CLK_NUM, }; +static int ap806_get_sar_clocks(unsigned int freq_mode, + unsigned int *cpuclk_freq, + unsigned int *dclk_freq) +{ + switch (freq_mode) { + case 0x0: + *cpuclk_freq = 2000; + *dclk_freq = 600; + break; + case 0x1: + *cpuclk_freq = 2000; + *dclk_freq = 525; + break; + case 0x6: + *cpuclk_freq = 1800; + *dclk_freq = 600; + break; + case 0x7: + *cpuclk_freq = 1800; + *dclk_freq = 525; + break; + case 0x4: + *cpuclk_freq = 1600; + *dclk_freq = 400; + break; + case 0xB: + *cpuclk_freq = 1600; + *dclk_freq = 450; + break; + case 0xD: + *cpuclk_freq = 1600; + *dclk_freq = 525; + break; + case 0x1a: + *cpuclk_freq = 1400; + *dclk_freq = 400; + break; + case 0x14: + *cpuclk_freq = 1300; + *dclk_freq = 400; + break; + case 0x17: + *cpuclk_freq = 1300; + *dclk_freq = 325; + break; + case 0x19: + *cpuclk_freq = 1200; + *dclk_freq = 400; + break; + case 0x13: + *cpuclk_freq = 1000; + *dclk_freq = 325; + break; + case 0x1d: + *cpuclk_freq = 1000; + *dclk_freq = 400; + break; + case 0x1c: + *cpuclk_freq = 800; + *dclk_freq = 400; + break; + case 0x1b: + *cpuclk_freq = 600; + *dclk_freq = 400; + break; + default: + return -EINVAL; + } + + return 0; +} + static int ap806_syscon_common_probe(struct platform_device *pdev, struct device_node *syscon_node) { @@ -54,76 +126,18 @@ static int ap806_syscon_common_probe(struct platform_device *pdev, } freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK; - switch (freq_mode) { - case 0x0: - case 0x1: - cpuclk_freq = 2000; - break; - case 0x6: - case 0x7: - cpuclk_freq = 1800; - break; - case 0x4: - case 0xB: - case 0xD: - cpuclk_freq = 1600; - break; - case 0x1a: - cpuclk_freq = 1400; - break; - case 0x14: - case 0x17: - cpuclk_freq = 1300; - break; - case 0x19: - cpuclk_freq = 1200; - break; - case 0x13: - case 0x1d: - cpuclk_freq = 1000; - break; - case 0x1c: - cpuclk_freq = 800; - break; - case 0x1b: - cpuclk_freq = 600; - break; - default: - dev_err(dev, "invalid Sample at Reset value\n"); + + if (of_device_is_compatible(pdev->dev.of_node, + "marvell,ap806-clock")) { + ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq); + } else { + dev_err(dev, "compatible not supported\n"); return -EINVAL; } - /* Get DCLK frequency (DCLK = DDR_CLK / 2) */ - switch (freq_mode) { - case 0x0: - case 0x6: - /* DDR_CLK = 1200Mhz */ - dclk_freq = 600; - break; - case 0x1: - case 0x7: - case 0xD: - /* DDR_CLK = 1050Mhz */ - dclk_freq = 525; - break; - case 0x13: - case 0x17: - /* DDR_CLK = 650Mhz */ - dclk_freq = 325; - break; - case 0x4: - case 0x14: - case 0x19: - case 0x1A: - case 0x1B: - case 0x1C: - case 0x1D: - /* DDR_CLK = 800Mhz */ - dclk_freq = 400; - break; - default: - dclk_freq = 0; + if (ret) { dev_err(dev, "invalid Sample at Reset value\n"); + return ret; } /* Convert to hertz */